Data Extraction Challenges
As SoC devices scale upwards in complexity and performance, extracting uncompressed data from a chip be-comes more challenging. It would require using a significant number of I/O pins. Or, the data would need designers with lots of patience, as a large amount of trace information would have to be transferred to memory in the probe pod.
To reduce the quantity of data that has to be transferred and minimize the amount of memory needed to hold the trace information, designers at EPI worked with the various processor suppliers. They developed an encoding scheme that employs a small amount of on-chip trace memory and still provides meaningful execution trace information. Both the Intel XScale and Lexra LX8000 series cores use this type of encoding scheme. This permits the trace data to come out of the cores and be transferred over the JTAG port to the MAJIC pod.
The MAJIC JTAG port can only handle multiple cores if the JTAG tap controller in each core is connected in a chain to a common JTAG interface on the SoC. Currently, the MAJIC hardware supports only JTAG communications to the on-chip debug circuitry. But the MAJICMX version will be able to interface to a wide variety of communications interfaces.
Data transfers over the JTAG port can take place at clock speeds from dc to 40 MHz. The MAJIC pod is equipped with both an RS-232 serial interface (1900 bits/s to 115.2 kbits/s), and a 10/100-Mbit Ethernet interface, to connect to the host computer that runs the main debug tools. The Ethernet interface lets the pod be used in either a shared or remote configuration. Five status indicators on the pod show the operational status of the emulator: power, status, run, connect, and Ethernet.
Once the MAJICMX pod is connected and the host computer is fired up and running the debug software and MDS2 tool suite, the pod is ready for action. For each processor core family on the SoC the tools will diagnose, a configuration kit must be installed. In most cases, one MAJICMX can have any number of configuration packages installed. Configuration kits will initially be available for ARM, MIPS, and Intel XScale processors. The kits will include support for the ARM9E and the Lexra LX5280 MIPS core, which both include some DSP capabilities. DSP core support will follow later this year. It will include cores from Texas Instruments, the DSP Group (Oak, Teak, Palm), Philips (Real16 and Real32), and the LSI Logic ZSP.
Price & Availability
The MAJICMX basic offering consists of the pod and one configuration kit (one CPU/DSP core family). It has a base price of $3995. A utility disk also comes with the kit. It includes a wide variety of initialization files, demo programs, a command-line debugger, and RDI/MDI dll files that will allow an RDI- or MDI-compliant debugger to work seamlessly with the pod. Additional configuration "kits" for various processors range in price from $1495 to $2995, depending on the processor.
A more complete bundle, which includes the company's host-based EDB source-level debugger, sells for $4995. In both cases, the user must provide a host PC to run the MDS2 software and debugger. The license for the EDB software requires the purchase of a license for each debug seat. For example, a customer designing an SoC with four ARM cores would license the MAJICMX with a CKM-01AM configuration kit, plus the EDB-ARM source-level debugger with four single-user licenses per debug station. (Or, a customer could purchase a four-user network floating license.) Additional EDB seats would cost $1995 each.
Embedded Performance Inc., 606 Valley Way, Milpitas, CA 95035; Lyle Pittroff, (408) 719-5600; www.epitools.com.