Minimizing PHY Output Delay
As seen from the previous discussion, one of the key factors in successfully designing robust SMIIs lies in providing tight control over the output delay characteristics of the PHY components. Because all system engineers don't have the extensive experience necessary to deal with these high-speed signal integrity issues from scratch, PHY component designers provide flexible solutions and tools for integrating SMII capabilities into system designs.
When driving the MAC ASIC from the PHY, if the spread of min-to-max delay is too wide, the interface design can run into problems on either one or both ends of the range. If the maximum delay is too large, it can create setup issues. Similarly, on the other end of the range, the inability to meet or exceed minimum PHY delay specifications can create problems with hold time issues at the ASIC end.
Even with a PHY delay time of 5.0 ns (at the high end of the acceptable specification), the required minimum of 1.5 ns for setup leaves very little headroom within the total 8-ns budget for trace delay and skew issues. For instance, designers using a typical PHY component that meets the stated specifications and a nominal circuit design with approximately 5- to 6-in. TX data traces can result in a negative setup margin. The bottom line is that under real-world conditions, simply meeting the specifications at the PHY end isn't enough to ensure a solid design.
Some of the newest PHY components address these issues with two features. The first feature, tight process control parameters, narrows the PHY-output range to exceed the stated SMII specifications. It thereby provides an additional headroom margin at the ASIC end.
The second emerging feature in new PHY devices is a built-in capability to adjust the center of the min-/max-delay range to meet specific design requirements. By attaching different values of capacitors to a specified pin on the PHY, an internal PLL can be adjusted precisely to shift the range either up or down.
For instance, with no capacitor attached, the default center is around 4.0 ns with a minimum of 3.0 ns and a maximum of 4.2 ns. If the system design called for the delay to optimally be centered at a lower point, however, then the designer could simply attach a capacitor with a value of 10 pF to shift to a 3.1-ns-centered range. Similarly, cap values of 30, 40, and 60 pF would shift the center to around 2.1, 1.8, and 1.0 ns, respectively.
Also with this adjustment feature, the output minimum and maximum delay spread is better controlled. For example, in a typical PHY, the output min-to-max delay can vary by a factor of around 2.0 to 2.5 ns, while this new feature can reduce the number to within a factor of about 1.5 ns. By preadjusting the PHYs' signal characteristics to precisely match the overall system requirements, designers avoid the risk of marginal timing versus the costs associated with adding complex clock management functions to the overall design. Plus, it helps reduce the need to adjust the clock traces in order to meet the setup-and-hold requirement, and it minimizes potential EMI issues.
A Straightforward Design
At the system level, the ability to precisely define and maintain robust delay and skew timing between the PHY and ASIC is a critical cornerstone in simplifying the overall design of multiport SMII switching systems. For example, creating a 32-port system can be relatively straightforward when implementing two 16-port ASIC switches and eight quad-PHY devices in a unified synchronous design (Fig. 5). The extra timing headroom provided by the PHY components enables the system to utilize a single clock buffer for driving all of the components. On the other hand, the more marginal timing associated with conventional PHY components could require significantly more complexity in the form of segregated clock buffers and/or precisely equalized clock traces.
In today's high-performance switch architectures, SMII is rapidly becoming another key enabling technology for reducing the pin count and the associated power requirements that have become so critical to achieving targeted port densities. In some instances, using simplified low-power SMII-optimized PHY components can reduce per-port power requirements by as much as 30% compared to traditional designs.
Essentially, designing for SMII at 125 MHz isn't a trivial challenge. It requires designers at both the system level and the component level to account for all critical signal-integrity issues. By leveraging the capabilities of new-generation integrated PHY components, however, system designers can shortcut many of the low-level timing issues while creating more robust multiport switching fabrics. As overall network architectures become more complex and demanding, these underlying SMII-based switching fabrics will provide a fundamental part of the continuing drive for higher port densities and lower-cost system capabilities.