High-performance microcontrollers (MCUs) crave bandwidth, which calls for moving new interconnect technologies like PCI Express, HyperTransport, Serial RapidIO, and Gigabit Ethernet on-chip. What will that mean in the long run? Enhanced performance. Reduced latency. Fewer support chips.
The problem of large pin counts has been countered with the switch to scalable, packet-oriented interfaces. These interfaces employ high-speed serializer/deserializers (SERDES), which turns out to be a benefit and a technical challenge when adding interfaces on-chip.
The challenge isn't as great for designers of 64-bit MCUs, who are well-versed in high-speed interfaces, as it is for those dealing with mid-range 32-bit MCUs. Still, technologies like PCI Express and Serial RapidIO will likely find their way into this computing space next year.
Part of the problem is that these new serial technologies gain their throughput numbers by pumping out data faster than the processor. For example, each PCI Express lane runs as 2.5 Gbits/s. Most embedded processors top out at 1 GHz.
So, it's not surprising that only the very high-end solutions like Intel's Pentium and Xeon and AMD's Athlon and Opteron employ wide serial interfaces. These solutions often are dedicated to applications such as graphics. But any MCU that incorporates the new interfaces will need SERDES technology that's a bit different from the core processing and other interface logic.
On the other hand, chip designers have to get these SERDES-based interfaces to work so developers have a well-tested chip at the ready. Of course, basic chip implementation isn't enough—board layout and power-supply design are also critical to a successful system design (see "PCI Express Design: A Lesson In Techno-Shock," ED Online 10174).
Interfaces available for today's MCUs are the aforementioned HyperTransport, Serial RapidIO, PCI Express, and Gigabit Ethernet. Each technology addresses different application areas, but logically, they have a lot in common.
With the exception of Ethernet, the interfaces use small packets and support multiple full duplex links. All are point-to-point interfaces that employ switches for expansion. And, they can support connection distances much larger than parallel bus technology.
Putting these interfaces on an MCU started with FPGAs (see "FPGAs: Hard And Soft Processors," p. 62). FPGAs will continue to provide a more flexible, although more expensive, solution compared to commercial-off-the-shelf (COTS) MCUs. Likewise, FPGAs are on the forefront of delivering high-speed, serial-interface support for the next generation while COTS chips push current standards.
Turning from parallel to high-speed serial interfaces does bring significant benefits. Chip pinouts have steadily increased as functionality and performance grows, and the lower pin count for the serial interfaces offers a respite. At the low end, a single lane lets devices fit into smaller packages. Moving up, the number of pins required for the serial interface still remains below parallel interfaces like PCI-X.
Added benefits of using serial interfaces are lower latency and different kinds of timing issues. In the latter, parallel interfaces must address clock skew issues due to the synchronized multiple signals. This tends to be a system designer's problem, whereas bit jitter associated with the serial interfaces tends to be the chip designer's—or more specifically, the SERDES designer's—responsibility. Typically, a developer using the chip has less concern for this problem when staying within the recommended design constraints.
Chip designers have to determine the amount of serial interface links to incorporate into a product. Obviously, adding links raises pin count and power requirements while adding connectivity and bandwidth. But the new point-to-point interfaces require multiple interfaces on-chip. Otherwise, a designer must use off-chip switches.
Switch chips are mandatory in large fabric-based designs (see "MCUs And Fabrics," p. 63). On smaller embedded applications, however, an MCU may be able to connect directly to a handful of devices. The latter simplifies system design and reduces the overall footprint.
There are benefits to restricting an MCU's serial interface to one connection. It simplifies the chip design. Also, when the chip is only connected to a single device and expandability using a switch chip is straightforward, system design becomes rudimentary. As it turns out, MCUs with high-speed serial interfaces tend to run the gamut.