PCI EXPRESS
The peripheral connectivity of the future, PCI Express is already replacing PCI and PCI-X interfaces in MCUs. PCI Express is showing up in high-end MCUs like those mentioned earlier. PCI Express channels often ratchet down to x1 links; x4 and x8 links are typical. Wider channels are often found on North Bridge chips for high-end processors versus MCUs.
The PCI Express architecture differs from HyperTransport and Serial RapidIO. PCI Express is a tree architecture rooted in a host interface, whereas HyperTransport and Serial RapidIO are a fabric of peers. As such, most MCUs will have a single host or client PCI Express interface.
Some MCUs will possess multiple host interfaces to communicate directly to a small collection of low-speed (relatively speaking) peripherals. Otherwise, a single host interface can easily handle multiple devices via PCI Express switches. A common configuration would be an MCU with a x4 PCI Express host interface that can be split into four x1 interfaces.
In a different approach, Applied Micro Circuits' 440SPe incorporates multiple PCI Express interfaces (Fig. 6). It features an x8 PCI Express host interface and dual x4 client interfaces. The 440SPe is designed to fit between one or more PCI Express host and PCI Express devices—an environment that's quite common in its target market of intelligent storage.
The 440SPe is finding homes in RAID and network-attached storage (NAS) systems, with a set of disks on one side and a processing system on the other. The latter may include many processors, but it's connected to the 440SPe using one PCI Express connection. Multiple connections provide redundancy and are often part of a dual cluster system.
Moving PCI Express into a fabric environment is possible with Advanced Switching Interconnect (ASI). ASI uses the same hardware interface as PCI Express. Intelligent ASI switches can detect and tunnel PCI Express host and client connections.
This won't change the way PCI Express is deployed on MCUs, but it will allow them to be used in a wider range of applications. Native ASI support within MCUs isn't expected for some time.
GIGABIT ETHERNET
Though Gigabit Ethernet has been popular, it doesn't scale like any of the other technologies. It's not possible to gang together multiple Ethernet links to provide higher bandwidth. Its latency and overhead is higher, too. Still, it provides MCUs with a link to a fabric that can span the world when using the Internet.
Ethernet offers the advantage of being ubiquitous. It's also available in a range of speeds, from 10BaseT up to 10Gbit Ethernet. Among its interesting options is Power over Ethernet (POE). This is less interesting within a confined fabric, but it proves useful in a local- or wide-area network.
Ethernet interfaces are available on-chip for MCUs as small as 16 bits. High-end MCUs often sport quad Gigabit Ethernet interfaces. On-chip Ethernet interfaces are common, though they tend to be used for networking applications instead of chip interconnects like HyperTransport, Serial RapidIO, and PCI Express/ASI. In fact, many chips that include Gigabit Ethernet often contain these interfaces as well.
Moving high-speed interfaces onto the MCU continues to make sense. These interfaces will begin to move down the food chain as more interface chips appear and as fabrics become more common. No designer would be surprised at an MCU with a PCI interface today. The same will be true for PCI Express and possibly RapidIO next year.
PCI EXPRESS
The peripheral connectivity of the future, PCI Express is already replacing PCI and PCI-X interfaces in MCUs. PCI Express is showing up in high-end MCUs like those mentioned earlier. PCI Express channels often ratchet down to x1 links; x4 and x8 links are typical. Wider channels are often found on North Bridge chips for high-end processors versus MCUs.
The PCI Express architecture differs from HyperTransport and Serial RapidIO. PCI Express is a tree architecture rooted in a host interface, whereas HyperTransport and Serial RapidIO are a fabric of peers. As such, most MCUs will have a single host or client PCI Express interface.
Some MCUs will possess multiple host interfaces to communicate directly to a small collection of low-speed (relatively speaking) peripherals. Otherwise, a single host interface can easily handle multiple devices via PCI Express switches. A common configuration would be an MCU with a x4 PCI Express host interface that can be split into four x1 interfaces.
In a different approach, Applied Micro Circuits' 440SPe incorporates multiple PCI Express interfaces (Fig. 6). It features an x8 PCI Express host interface and dual x4 client interfaces. The 440SPe is designed to fit between one or more PCI Express host and PCI Express devices—an environment that's quite common in its target market of intelligent storage.
The 440SPe is finding homes in RAID and network-attached storage (NAS) systems, with a set of disks on one side and a processing system on the other. The latter may include many processors, but it's connected to the 440SPe using one PCI Express connection. Multiple connections provide redundancy and are often part of a dual cluster system.
Moving PCI Express into a fabric environment is possible with Advanced Switching Interconnect (ASI). ASI uses the same hardware interface as PCI Express. Intelligent ASI switches can detect and tunnel PCI Express host and client connections.
This won't change the way PCI Express is deployed on MCUs, but it will allow them to be used in a wider range of applications. Native ASI support within MCUs isn't expected for some time.
GIGABIT ETHERNET
Though Gigabit Ethernet has been popular, it doesn't scale like any of the other technologies. It's not possible to gang together multiple Ethernet links to provide higher bandwidth. Its latency and overhead is higher, too. Still, it provides MCUs with a link to a fabric that can span the world when using the Internet.
Ethernet offers the advantage of being ubiquitous. It's also available in a range of speeds, from 10BaseT up to 10Gbit Ethernet. Among its interesting options is Power over Ethernet (POE). This is less interesting within a confined fabric, but it proves useful in a local- or wide-area network.
Ethernet interfaces are available on-chip for MCUs as small as 16 bits. High-end MCUs often sport quad Gigabit Ethernet interfaces. On-chip Ethernet interfaces are common, though they tend to be used for networking applications instead of chip interconnects like HyperTransport, Serial RapidIO, and PCI Express/ASI. In fact, many chips that include Gigabit Ethernet often contain these interfaces as well.
Moving high-speed interfaces onto the MCU continues to make sense. These interfaces will begin to move down the food chain as more interface chips appear and as fabrics become more common. No designer would be surprised at an MCU with a PCI interface today. The same will be true for PCI Express and possibly RapidIO next year.