One modern RTOS that implements memory protection is Enea OSE. It incorporates a memory-management system (MMS) that works with a PowerPC's memory-management unit (MMU) to provide separate memory spaces for running processes. It also gives them a method of interprocess communication. OSE processes can be grouped together into blocks that provide a finer degree of control over memory use. A block can have its own local memory pool. That way, if a block pool is corrupted, only the processes located within it are affected.
That interprocess-communication mechanism is consistent with OSE's philosophy of protecting executing processes. Rather than using shared memory spaces, it implements a message-passing mechanism that involves kernel calls. Memory or message ownership is never shared.
A different approach to dynamic reconfiguration is taken by the QNX RTOS. Device drivers aren't kernel processes. Instead, they run in user space. This makes it easy to start up and kill device drivers. A watchdog program can detect the removal or insertion of a card and automatically run or kill the driver process. Unlike other operating systems, it doesn't make the user rebuild the kernel and reboot the system when adding a driver.
Processor cards can be changed during operation with the QNX Neutrino kernel. Just place the processors on separate hot-swap interfaces, such as a CompactPCI card, and make sure there's a way to bootstrap the new card's kernel. It also supports SMP using Intel processors.
Hot-swap board designs are changing and developing every day. Growth in data access and exchange across computer networks and the Internet has driven up the need for high-availability and high-performance servers. Those servers are leading a development of new interfaces that will support hot swapping. Computer I/O, particularly data storage, is one area pushing hot-swap board designs ahead.
The Intelligent I/O initiative, or I2O, was among the first attempts to simplify I/O device connectivity by orders of magnitude. The actions of the operating system would be decoupled from those of the device providing the data. By separating the operating system's abstract I/O requests from the physical execution of the request, I2O made it easier to design a hot-swap interface that didn't impact the OS directly. The specification defined an I2O embedded processor, in this case the Intel i960, along with an RTOS that handled the details for card insertion and removal.
Any processor and bus interface might be applied, however, because I2O doesn't define the I/O hardware architecture. Its initial design assumed that the PCI bus was the data-transport mechanism. The bus then became the I/O bottleneck.
Other I/O architectures were then invited into the scene, including next-generation I/O (NGIO) and future I/O. Both hope to define a low-latency serial architecture for PC server I/Os at data rates of 1 Gbit/s. They envision a network of point-to-point serial connections between the various devices and the operating system, in which each device gets 100% of the bandwidth. These connections will be controlled by data switches.
Next-generation PCI designs, such as PCI-X, also are vying for a role in fast I/O. They have the advantage of existing hot-swap designs. The local bus has basically become the norm in all PC-based platforms. It has a strong following in applied computing as well.
This popularity rests in PCI's processor-independence, low-pin-count interface, and scalability up to 64-bit I/O performance. It provides today's most popular connectivity standard for a variety of peripheral devices. Motorola, for example, supports the PCI hot-swap version 2.1 specification on cards like its CPV5350 (Fig. 3).
Even while preserving these features and its backward compatibility, PCI keeps evolving. Version 2.2 includes hot-plug capability that's implemented on the host, making most existing PCI cards capable of insertion and removal without shutting down the host platform.
On paper lately, it's looked like InfiniBand is the hot-swap technology of the future. InfiniBand is a channel-oriented, switched-fabric, serial-point link I/O architecture for high-performance and high-availability data access. It derives high performance from an I/O engine that's coupled directly to host memory. Shared-bus architectures are replaced by a fabric of switchable point-to-point links.
This approach removes the CPU from the I/O subsystem. The CPU can then communicate with peripherals asynchronously. The I/O channel engine is responsible for moving data to and from main memory. By functioning as a switch, the bus enables point-to-point links to scale with improvements in the performance of CPUs, memory, and peripheral devices.
For increased reliability and a better basis for hot-swap approaches, InfiniBand supports separate fault domains for the CPU complexes and I/O units. At the same time, it handles reliable connection mechanisms, data integrity, and fault tolerance. The failure of any unit in the fabric doesn't impact the remaining nodes. The first InfiniBand-compliant products should begin to appear during 2001.
Hot swapping will never be a requirement for all embedded systems. Even with standardization efforts, a greater array of solutions, and the lower costs that come with more design alternatives, it won't become a staple. There will always be those systems that don't have the availability or live upgradability requirements to justify it.
But as costs come down and technologies become more reliable, more and more systems will be able to use hot-swap standards. Hardware interfaces are gradually being defined for recognizing the insertion and removal of cards. To start meeting these specifications, vendors are building products (see "The Route To High-Availability Networking," p. 100).
CompactPCI will clearly take the forefront in hot-swap designs, with an established and popular interface, along with working products, supporting the specification. Nonetheless, other standards are emerging, especially for mission-critical I/O applications. The result will be a solidification of hot-swap standards, better software support, and a greater variety of implementations for building high-availability and fault-tolerant systems.