Continuous change in network speeds and services has forced network equipment designers and network-processor (NP) vendors to re-evaluate their designs. The quest is on for new and better ways to handle not only the higher speeds, but also the ever-increasing amount of network traffic.
Earlier generations of NPs or network-processing units (NPUs) were inadequate for line speeds greater than about OC-12 (622 Mbits/s). To meet the needs of those designing switches, routers, remote access servers, and other equipment for 1-Gbit/s and 10-Gbit/s Ethernet and Sonet OC-48, OC-192, and OC-768, designers are resorting to various new approaches, as semiconductor vendors provide a rich new mix of products and solutions.
An NP is a chip or chip set that performs packet processing at line speed. It may be a programmable RISC CPU, or multiple CPUs optimized for packet processing. An NP might also be one or more ASICs, a specialized chip, or a collection of chips that perform the desired functions. NPUs work at layers 2 through 7 of the OSI reference model. Earlier routers and switches worked at layers 2 and 3. But the growing number of new services, such as quality of service (QoS), differentiated services, and multiprotocol label switching (MPLS), now require processing through layer 7. Longer packets that take more time to classify and process have resulted. Moreover, with line speeds increasing at a rate faster than Moore's Law updates CPU chips, processing packets at line speeds has become excruciatingly difficult.
An NP is a basic component of a typical router or switch in a line or port card (Fig. 1). The card includes the physical (PHY) layer, usually fiber optic components with appropriate serializer/deserializer (SERDES) transceivers. This is followed by a framer that deals with the specific protocol used, such as Ethernet, Sonet, and ATM. The resulting packets are sent to the processing circuits. The switch fabric follows them and connects the line card to other line cards. This is called the datapath or data plane. Note the bus connection, usually PCI, to an embedded RISC processor, which implements the control path or plane.
The data plane functions are:
- Pattern matching and packet classification
- Packet processing or data modification
- Traffic or queue management and traffic shaping
- Security
The control plane functions are:
- Set-up/tear-down
- Table updates
- Register/buffer management
- Exception handling
- Statistics gathering
Circuits in earlier equipment using one or more fast custom ASICs performed packet processing at line speed (Fig. 2a). Although still valid today, this approach lacks flexibility, but it remains the best for achieving line speeds of OC-192 and up.
If the processor is fast enough, it can handle all datapath processes described above using an NPU (Fig. 2b). Current processors can handle line speeds up to about OC-12, with OC-48 on the way.
In the newest configuration, an NPU performs many of the operations. Several complex and time-consuming operations are offloaded and delegated to coprocessors or specialized chips, typically content-addressable memory (CAMs) for packet search and classification and traffic manager chips. Most current designs use this method (Fig. 2c).