Network Processors Take The High Road... And The Low Road

Another classification coprocessor designed for OC-192 speeds, Solidum Systems' PAX.port 1100, integrates 16 classification engines. The engines are programmed using a high-level, nonprocedural pattern description language (PDL). Protocol libraries are available. Bandwidth is independent of the number of classification entries.

A cryptographic accelerator designed by Chrysalis-ITS meets FIPS 140-1 level 3 requirements. The Luna 340 packs four RISC processors on the chip. It supports dozens of private- and public-key encryption algorithms. Also, it can sustain OC-3 rates for IPSec-ESP and ATM encryption. The Luna 340 can handle bulk DES encryption at Gigabit Ethernet speeds, as well.

Two standards organizations may help bring some order to the market. Most of the companies in the network-processor space are a member of one or both organizations.

The Common Switch Interface Forum was started to support multivendor interoperability for an OC-192 signaling system known as CSIX. This system doesn't use out-of-band signaling. It's a board-level definition that allows network-processor and support chips from different sources to be connected with minimal support.

The second group is the Common Programming Interface (CPIX) Forum. CPIX's goal is to promote application-programming interfaces (APIs) between control and network processors. It will be interesting to see how successful CPIX will be, given the architectural diversity of network processors.

These network processors cover a lot of ground. But it's clear that designers will have a number of models to choose from, regardless of the target market for their switch design. The flexibility offered by network processors will let vendors distinguish their products while enhancing software.