A PCI-To-PCI Bridge
Many members of the StarGen management and design team became experienced with PCI buses by working for the PCI bridging group of Digital Equipment Corp., and they have built that PCI bridging experience into StarGen. In effect, the whole StarGen endpoint-to-endpoint connection (endpoint to switch node....to switch node....to endpoint) is a PCI-to-PCI bridge, although this is typically a bridge from a PCI system to a nontransparent PCI device, as the far PCI connection is usually a different PCI system.
The basic StarGen switch node supports six ports. Each port drives up to 5 Gbits/s of bandwidth, or 625 Mbytes/s, with half in each direction. To be fair, however, in a typical six-port switch situation, three ports each connect to the other three ports, forming three connections through the switch. This means that overall operational bandwidth through the switch will be 15 Gbits/s or 1.875 Gbytes/s. A multicast to five ports would up node bandwidth to 9.375 Gbytes/s. Every port is made up of four LVDS, bidirectional, 622-Mbit/s differential pairs and can drive up to five meters of unshielded copper cables. Additionally, these ports are hot-plug capable.
StarGen's port bandwidth exceeds PCI bandwidths. To take advantage of the StarGen fabric, a PCI-endpoint implementation needs multiple switch-node layers to multiplex the slower PCI ports into the faster StarGen ports.
StarGen really shines as a backplane itself. Its ports can be mapped to the CompactPCI backplane to form a full StarGen backplane with 24 ports on the J1 through J5 connectors, and a collective potential bandwidth of 45 Gbytes/s for a very high-performance data-transfer backplane for data-gathering and MP operations.
StarGen projects that its Star switch chips will be sampling by the second quarter of next year. Packaged in a 272-ball plastic BGA, every chip dissipates approximately 2.5 W. They will sell for less than $50 each in 1000-unit lots.
Virtual PCI As A Ring
GigaBridge also implements a Virtual PCI connection subsystem, but on a very different hardware base (Fig. 4). It builds on a dual counter-rotating ring, which has built-in fail-safe redundancy. This capability permits the hardware to lock out a failing endpoint on the ring and still continue functioning. Plus at the board level, a GigaBridge also supports PCI and CompactPCI hot-swapping. The offending board can be hot-swapped out and replaced, enabling the system to recover to full operation. Alternatively, GigaBridge could be deployed as an on-board technology to interconnect high-performance elements on a board.
GigaBridge is fully PCI compatible. It provides a Virtual PCI adjunct bus to systems using PCI. It acts like a PCI bridge and is compatible with existing PCI system software. Every ring node can drive up to four PCI bus slots.
Interestingly, GigaBridge is being fielded by PLX Technology, another PCI bridge chip vendor. Originally, GigaBridge was developed as the Sebring Ring, featuring a dual counter-rotating ring. Each of these rings clocks at 400 MHz, with 16-bit LVDS pairs. The basic media bandwidth is 800 Mbytes/s per ring. But unlike a parallel bus, which can only hold one active transaction on its hardware bus, GigaBridge can accept multiple transactions due to its ring structure.
A node on a ring can insert a transaction when the ring at that point is unoccupied. That transaction moves down the ring until it reaches its destination, where it's taken off the ring medium, or else it returns to its sender. If the system is designed so that the source and destinations on the ring are fairly close together, a source-to-destination transaction won't take much of the ring's resources, leaving room on the ring for multiple transactions. (Think of a ring as a circular plastic tube with tennis-ball transactions moving between node stations, except that these can be elongated tennis balls. The space between the tennis balls is open to accepting a new transaction, or a new tennis ball.)
As a result, the ring can hold multiple transactions. PLX claims that the ring can support up to four simultaneous transactions, depending on how close the source nodes are to their destination nodes on the ring. Given the nature of many telecommunications and data-communications front-end applications, this may not be a bad assumption, as these tend to be data-flow applications, moving data through the system to be processed in a regular manner. Assuming that four concurrent transactions can be inserted on each ring (eight transactions for two rings), GigaBridge can deliver a 6.4-Gbyte/s bandwidth.
GigaBridge supports connections to 32-bit, 33-MHz or 66-MHz PCI. Assuming an average of four simultaneous PCI transactions per ring, the dual counter-rotating ring can support up to 48 32-bit, 33-MHz PCI connections. But PCI is relatively inefficient, enabling even more PCI connections on the ring, depending on system latency requirements. The GigaBridge system has built-in addressing to support up to 224 PCI bus segments with up to 896 PCI slots.
PCI connections to the ring, called nodes, can belong to a cluster, with up to 32 nodes sharing a cluster ID. Ring nodes are able to communicate over the ring with other nodes in their cluster. The only other communicating taking place on the ring is to their nearest neighbor, the next node down on the ring. The ring clusters also support up to seven domains. These are separate PCI address spaces that support a separate PCI host, each with a protected 64-bit address space. This is good news for MP applications that require separate independent processor spaces.