Novel Architectures Pack Multiple DSP Cores On-Chip (Part 1)

Tough Programming
Programming such multicore designs isn't a trivial job. It takes a whole new way of thinking. "Unlike programming and controlling a single-core solution, multiple cores must be treated as separate devices," notes Charlie Mera, director of marketing at Agere Systems. "Whether it's a parallel processing or a pipelined problem, each core must be treated as a single entity when writing your application code. Never try to spread the cycle-by-cycle processing of an application or thread across multiple cores," he adds.

"In parallel processing, for instance, the user can share the application code and peripherals," Mera explains. Because memory and peripherals dominate the size and cost of any DSP, this approach has significant cost advantages. In a pipelined approach, the architecture facilitates efficient exchange of data and communications between the cores in the chain. "The key decision or challenge for either case is to decide how you want to control the subsystem—centralized, where one core manages all of the resources, or distributed, where each core is involved in controlling the resources," he asserts.

According to Agere, the multicore Starpro2000 has a suite of development tools, from a compiler to an assembler/linker, to a device simulator, to fully support it. Currently, Agere is in the process of integrating OSE's Illuminator to support task aware debugging.

As the company prepares to take the Starpro2000 into production by mid-2002 in 0.13-µm CMOS, it also is evaluating a future Starpro member with built-in coprocessors, smarter peripherals, and an improved memory hierarchy.

See associated table.