Performing 2.7 billion instructions per second (BIPS), this new class of access communications processor combines 16 166-MHz DSP cores and five
RISC processors on the same chip (Fig. 3). Unlike conventional DSP cores,
each core in this 4-by-4 array uniquely combines scalar and vector processing. Plus, it offers room to run user software.
In similar moves last year, PMC-Sierra grabbed fabless developer Malleable Technologies to gain access to its multi-core Meca DSPs for voice-over-packet applications. Intel also brought VxTel’s multicore capabilities on-board. Integrating all DSP and packet processing functions on the same die, Meca can replace more than 10 conventional general-
purpose DSPs in any application today, PMC-Sierra claims.
Leveraging their core competency, many leading providers of licensable
DSP cores have joined this fray. In conjunction with Tality and HelloSoft, BOPS has readied a system-on-a-chip (SoC) solution, called VoiceRay, with a prepackaged application for a carrier-class VoIP gateway. While HelloSoft offers the application software for the VoiceRay chip, Tality provides SoC implementation services.
BOPS’ VoiceRay incorporates a set of eight fundamental cores and a 64-bit MIPS RISC engine to attain 192 channels of G.729a or 512 channels of G.711, both with 32 ms of echo cancellation on a single chip. The RISC CPU does the housekeeping and manages the traffic to each of these cores (Fig. 4). Each basic core in this design is a scalable ManArray-based 1x2 (PEs) fixed-point core, wherein each PE is a five-way indirect very-long-instruction-word (iVLIW) architecture.
In addition, the fundamental 1x2 core employs a single-instruction, multiple-data (SIMD) format to provide a high level of built-in parallelism. While the cluster switch buried inside of each core provides interprocessor communications, the on-chip DMA engine, coupled with control and data buses, enables communications between the RISC processor, the cores, and the peripherals.
"Our SoC intellectual property is licensable and synthesizable, allowing the user to take it to the foundry of choice," notes Zafar Malik, vice president of SoC design services at BOPS. "Therefore, by porting it to the right process technology, the user can achieve an optimum combination of size, power, and cost. By providing a licensable SoC in a box, BOPS has taken the IP game to the next level."
"As designers pack large numbers of cores on a single chip, the software task partition, system bus bandwidth, efficiency, and external memory band-width play a more critical role than the DSP core’s performance," explains Kan Lu, chief technical officer at 3DSP, a
maker of configurable DSP cores. Combining a modular (loosely coupled)
approach with proprietary SP-5 super-SIMD cores and a shuttle bus controller, 3DSP has developed an eight-core SoC for VoIP gateways. Designed for a network company, this VoIP SoC handles 768 channels with 128 ms of echo cancellation. Maximum power consumption for this device is 2.1 W, when the SP-5 core runs at a 280-MHz clock.
Concurrently, National Semiconductor is prepping a configurable SoC for
3G cellular handset applications employing multiple SP-5 cores and other
system-level IPs that the company has obtained by acquiring Algorex in
December of 1999. Using 0.18-µm CMOS, the supplier expects to see prototypes of its new baseband chip before year’s end and hopes to supply them to key customers by early next year.
Likewise, RealChip Communications has licensed Infineon Technologies’
carmel DSP core to build a multicore VoP solution on a single chip. Backed
by applications software and a complete toolset, RealChip is confident that its SoC devices will enable convergence of voice, video, and data over packet-based networks.
Configurable Methodologies
Although the building block cores deployed in these multicore DSP SoCs
offer some degree of flexibility and programmability, they’re not customizable and configurable. But that scenario is changing rapidly as licensable core developers, like ARC International, Improv Systems, QuickSilver Technology, and PACT, unwrap configurable methodologies for DSPs. They believe that configurable methodologies will alter the DSP landscape.
Improv, for example, has generated a programmable system architecture
based on its configurable VLIW core, called Jazz. "Our platform is programmable, scalable, and configurable," notes Bob Bell, director of marketing at Improv. A key feature of this core is that it permits a designer to add custom instructions and/or execution units via the PSA composer tool suite. According to Improv, the Jazz PSA platform is fully
supported by a Java-based development system and an advanced compilation
system that provides system partitioning, memory allocation, code generation, and optimization.
Likewise, ARC has developed a user-customizable 32-bit RISC processor
with DSP extensions, letting the user modify and extend the architecture for specific applications. One early adopter of this architecture for multiprocessor design is Hyperchip. Packing 16 ARC cores on-chip, Hyperchip has developed a petabit networking router.
Combining the best of both microprocessor and DSP capabilities with
massively parallel processing on the same chip, PACT has readied a dynamically reconfigurable DSP engine with unprecedented performance and bandwidth. Comprising an array of 128 PEs on-chip, this extremely parallel reconfigurable 32-bit core can perform over 50 BOPS, while consuming only one-tenth the power of leading DSP designs, claims Martin Vorbach, PACT’s co-founder and chief technology officer. PACT hopes that the XPU128 will be used in conjunction with a DSP core in a multicore SoC solution for emerging 3G and 4G wireless basestations and other compute-intensive high-bandwidth applications.