Power-Management ICs Are Ideal For DDR-SDRAM Memories

Double-data-rate, single-data random access memory (DDR-SDRAM) has become popular in desktop and portable computing. The reason is its superior performance, low power dissipation, and competitive cost compared to other memory technologies.¹

DDR initially had a 266-Mbyte/s data rate versus a 133-Mbyte/s data rate for plain SDRAM. Subsequently, the DDR data rate has increased to 400 Mbytes/s. A second-generation DDR, or DDR2, debuted at the beginning of 2004. This extended the data rate from 400 up to 667 Mbytes/s, while reducing power consumption further.²

First-generation DDR still dominates the market, but DDR2 is gaining market share fast. Additionally, a transition crossover is expected by the end of 2005. But no matter the flavor, DDRx memories require a new and more complex power-management architecture compared to the previous SDRAM technology.

DDR POWER-MANAGEMENT ARCHITECTURE
Figure 1 illustrates the basic power-management architecture for first-generation DDR memories. In DDR memories, the output buffer is a push-pull stage, while the input receiver is a differential stage. This requires a reference bias midpoint, V_REF, and consequently, an input voltage termination that can source, as well as sink, current.

This last feature (sourcing and sinking current) differentiates the DDR V_TT termination from other terminations present in the PC motherboard. This difference is especially noticeable in the termination for the front system bus (FSB) that connects the CPU to the memory channel hub (MCH), which requires only sink capability due to termination to the positive rail. Hence, such DDR V_TT terminations can't reuse or adapt previous V_TT termination architectures, and they require a new power design.

The logic gates in first-generation DDR memories are powered from 2.5 V. Be-tween any output buffer from the chip set and the corresponding input receiver on the memory module, we typically find a routing trace or stub that needs to be properly terminated with resistors RT and RS (Fig. 1, again). When all impedances (including that of the output buffer) are accounted for, each terminated line can sink or source ±16.2 mA.³ For systems with longer trace lengths between transmitter and receiver, it may be necessary to terminate the line at both ends, doubling the current.

The 2.5-V V_DDQ required for the DDR logic has a tolerance of +200 mV. To maintain noise margins, V_TT must track V_DDQ. It has to equal V_DDQ/2, or approximately 1.25 V, with an accuracy of ±3%. Finally, V_REF must equal V_TT to +40 mV. These tracking requirements, plus the requirement that V_TT can both sink and source current, present unique challenges in powering DDR memory.

WORSE-CASE CURRENT CONSUMPTION
—VTT Termination: Assuming the following structure for a 128-Mbyte memory system:

128-bit wide bus
8 data strobes
8 mask bits
8 V_CC bits
40 address lines (2 copies of 20 addresses)

192 lines

With each line consuming 16.2 mA, we have a maximum current consumption of:

192 × 16.2 mA = 3.11 A peak-V_DDQ Power Supply: V_DDQ sources current during the phase in which V_TT sinks current. It follows that the current for V_DDQ is unipolar, and its maximum equals the maximum value required of V_TT, 3.11 A.