Power-Management ICs Are Ideal For DDR-SDRAM Memories

DUAL PWM CONTROLLER
A variety of DDR power ICs is on the market. There are the ML6553/4/5 with integrated MOSFETs; the FAN5066 for high-power systems; and the FAN5068, a combo DDRx and advanced configuration and power interface (ACPI). Another device, the FAN5236, is specifically designed for all-in-one powering of DDRx memory systems. This single IC integrates a switcher controller for V_DDQ, a switcher controller for V_TT, and a linear buffer for V_REF. The switcher for V_DDQ runs off any voltage in the range from 5 to 24 V. However, the switcher for V_TT is different. It's designed to run from the V_DDQ power and switches synchronously with that switcher.

Both switchers' outputs can range from 0.9 to 5.5 V. Because the bus lines are driven with 2.5 V (DDR) or 1.8 V (DDR2) for V_DDQ and are terminated to 1.25 V (DDR) or 0.9 V (DDR2) for V_TT, the power to some extent circulates between V_TT and V_DDQ. Drawing V_TT from V_DDQ minimizes total circulating power, and thus circulating power losses. The V_TT switcher also can be shut down for standby mode.

DUAL PWM CONTROLLER APPLICATION
Figure 2 shows the typical application and the table shows the associated bill of materials (BOM) for a 4-A continuous, 6-A peak V_DDQ application. (For the table of the associated bill of materials, go to www.elecdesign.com and see Drill Deeper 10926.) Note that in Figure 2, the outer rectangle represents the FAN5236 dual pulse-width modulator (PWM), while the two smaller rectangles named PWM1 and PWM2 represent the two switchers inside the IC. Also note that in the table, the FAN5236 is called DDR controller and referenced as U1. This circuit can easily be modified to set V_DDQ at 1.8 V (via divider R5/R6) and V_TT to 0.9 V for DDR2 applications.

Setting The Output Voltage: The internal reference of the FAN5236 PWM controller is 0.9 V. The output is divided down by a voltage divider to the VSEN pin (R5 and R6). The output voltage therefore is:

0.9 V/R6 = (V_DDQ ×; 0.9 V)/R5

Output Inductor Selection: The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The standard practice is to choose minimum current of somewhere between 15% and 35% of the nominal current. At light load, the controller can automatically switch to hysteretic mode of operation to sustain high efficiency. The following equations help to choose the proper value of the output filter inductors, L1 and L2.

where DI is the inductor ripple current and ?V_OUT is the maximum ripple allowed.

L = [(V_IN -­ V_OUT)/(F_SW × DI)] × (V_OUT / V_IN)

where F_SW is the switching frequency.

Output Capacitor Selection: The output capacitors, C6 and C8, serve two major functions in a switching power supply. Along with the inductor, it filters the sequence of pulses produced by the switcher, and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, inductor ripple current (DI), and the allowable ripple voltage (DV).

ESR DV/DI

Input Capacitor Selection: The input capacitor (C1) should be selected by its RMS current rating. In DDR mode, the V_TT power input is powered by the V_DDQ output. Therefore, the V_DDQ converter load I_OUT produces the input capacitor ripple current. The RMS input current will be:

I_RMS = I_OUT(MAX)√D — D²

where D is the duty cycle of the PWM1 converter and is calculated as D = V_OUT/V_IN. In parallel to C1 is C9, a small ceramic capacitor always present at the input for high-frequency source-impedance filtering.

Power MOSFET Selection: Losses in a MOSFET are the sum of its switching (P_SW) and conduction (P_COND) losses. In typical applications, the FAN5236 converter's output voltage is low with respect to its input voltage. Therefore, the lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should thus be selected to minimize conduction losses, thereby selecting a MOSFET with low R_DS(ON).

In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, lessening the impact of its conduction loss. Q1, however, sees most of the switching losses, so Q1's primary selection criteria should be gate charge.

Layout Considerations: Even during normal operation, switching converters produce short pulses of current that could cause substantial ringing and electromagnetic interference if layout constraints aren't observed. Two sets of critical components exist in a dc-dc converter. The switching power components, which process large amounts of energy at high rates, are noise generators. The low-power components responsible for bias and feedback functions are sensitive to noise. A multilayer pc board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane, and break this plane into smaller islands of common voltage levels. For details, refer to the FAN5236 data sheet.

FUTURE TRENDS
As has been the trend for many years, customers will demand more and more memory to run their ever-larger software applications. Systems such as Intel's boards for servers are already being designed with large amounts of DDRx memory. Some systems contain as much as 16 Gbytes. To power such systems, the decreased power requirements of first-generation DDR may still not be adequate, hence the move toward DDR2 memory technology.

Though we're reaching the peak of the DDR2 cycle, the industry is already buzzing about the next-generation memory technology for PCs—DDR3 memories. While DDR3 isn't expected to reach the market until 2006, vendors like Samsung have already shown prototypes of 512-Mbyte DDR3 DRAM chips, increasing speeds up to 1066 Mbits/s while reducing the voltage down to 1.5 V.

References:

1. JEDEC STANDARD JESD79, June 2000 and JESD8-9 of Sept. 1998.
2. JEDEC STANDARD JESD79-2A, January 2004.
3. DDR SDRAM Signaling Design Notes; Micro Linear and Micron Technology; April 1999.
4. Wang, Ling Ling, and Leung, Philip of Acer Labs; Tabrizi, Farhad of Hyundai Microelectronics, "DDR DRAMs Pare Down Power for Laptop," Portable Design, July 2000.
5. DDR2 low power features. Samsung AN. 10-18-2003.