A second major POSIC benefit is that it performs on-chip packet preclassification and tagging. This relieves external processors from having to analyze every packet in the system and making link-layer and buffer-management functions more efficient, freeing them for higher-priority processing. This feature increases the bandwidth for packet processing and queue management, guaranteeing the quality of service (QoS) so essential in today's systems.
POSIC's programmable frame-tagging engine allows networking system software to specify particular patterns in an incoming packet and direct POSIC to preclassify packets based on different bit fields inside of the packets. Preclassification eliminates the need for the host CPU to process every packet on every line card and helps to streamline switch-fabric operations to improve processing and system capacity.
Frame-tagging applications include PPP parsing, data/control packet separation, placing data/control packets in different buffers, looking up MAC addresses to determine if a packet belongs to the node, prioritizing packets in different priority queues, and identifying incoming MPLS labels. Frame tagging works over both packets and ATM cells.
In addition, POSIC further ensures efficient traffic engineering in systems using multiprotocol level switching (MPLS). It handles all parsing and label lookup for MPLS packets on-chip.
Finally, POSIC supports a wide range of new and proposed packet-framing protocols, including Lucent's Simple Data Link (SDL or ITEF rfc 2823), Nortel's Data Over Sonet (DOS or ANSI T1X1.5), and Cypress' own Hybrid Data Transport (HDT) protocol. The POSIC chip's generic optical network protocol framer delineates all of these types of packets with packet length and CRC information. This positions POSIC for use in virtually all next-generation networks.
POSIC contains over 3 million 0.18-µm CMOS transistors housed in a 504-pin BGA package. It does a lot more than simply perform the usual Sonet housekeeping chores (Fig. 2).
POSIC talks to the CY7B9532V transceiver over two 16-bit data buses using HSTL signaling. Transceiver-side processing includes Sonet framing and de-framing, as well as section, line, and path overhead (SOH, LOH, POH) processing. Sonet framing can be bypassed in applications where data is transmitted directly over fiber in a non-Sonet form.
Next, virtual-concatenation logic allows the data to be transmitted and placed into multiple Sonet SPEs, or removed from SPEs in its original protocol format. This sophisticated logic manipulates the Sonet/SDH overhead bytes so that different packet sizes and types can be mixed as necessary. In addition to standard Sonet formatted data, POSIC can handle ATM, Ethernet, and other types of packets. It permits the transmission and recovery of packets that are larger than the standard SPE too.
Inside the POSIC chip are three transmit and receive processors called engines—an ATM engine, an HDLC engine, and a generic protocol engine. These processors handle all packet assembly and disassembly, formatting, and the related chores.
In the receive path, a programmable frame-tagger engine identifies and tags packets. The engine parses and sorts the packets, appends a tag, and stores the tag in a buffer for use by the external processor as desired.
The protocol determines the interface to the LAN/MAN/WAN side of the chip. In ATM systems, a 32-bit UTOPIA bus is employed, as defined in the ATM standards. For other packet protocols, such as Ethernet and HDLC-like formats, a 32-bit POS-PHY bus is used. A separate 32-bit bidirectional bus is provided for the external processor.
Price & Availability
The CY7C9536V POSIC chip will be available in sample quantities in June. Full production is expected during the third quarter. It's priced at approximately $335 each in quantities of 1000.
Cypress Semiconductor Corp., 3901 N. First St., San Jose, CA 95134; (408) 943-2600; www.cypress.com.