The Drive To Higher Performance: Building on the popular Virtex FPGA family, Xilinx's recently unveiled Virtex II Pro series of FPGAs enhances the performance and integration levels. The top-of-the-line XC2VP50 will pack about 50,000 logic macrocells (each macrocell is equivalent to about 40 logic gates) for a total gate count of about 2 million. It also will contain four PowerPC405 32-bit CPU cores that can operate at 300 MHz, letting the chip deliver a compute throughput of over 1200 MIPS (Fig. 2). Though not as abundant as on the Stratix devices, the static RAM integrated on the Virtex II Pro will top out at 3.8 Mbits.
But designers at Xilinx have gone several steps further in the I/O and compute areas. For starters, they integrated 16 high-speed serial transceivers (3.125 Gbits/s each) licensed from Mindspeed (a Conexant company). Each I/O channel contains a complete set of user-configurable support circuits that include 8B/10B encoding and decoding, channel aggregation, and support for improved signal integrity across varying pc-board metal trace lengths. The use of the high-speed serial channels as a bus replacement would then save a significant number of I/O lines, simplifying the pc-board design and reducing electromagnetic interference.
Other resources on the Virtex II Pro chips include 168 18- by 18-bit multipliers to accelerate various signal processing algorithms, as well as a dozen PLLs for accurate and stable timing.
To integrate all these features, Xilinx's designers employed one of the most advanced 0.13-µm manufacturing processes yet released for commercial use. The resulting Virtex II Pro chips are the first to combine both hard processor cores and the multiple 3.125-Gbit/s serial channels. As part of the array architecture, the designers incorporated a segmented routing scheme they created called active interconnect. This scheme will ensure predictable performance, permitting the design tools to deliver consistent results.
Designers also put the nine metal layers to good use. The first four levels of copper metallization are used to connect the logic that forms the processor cores and tie those cores into the rest of the chip. This way, the hard core IP blocks are "immersed" in the metallization and deliver their best performance to the rest of the chip. The remaining five metal layers are used to route signals be-tween the cores and the user-configurable programmable logic region.
Though Actel's just-released ProASIC Plus family just passed the megagate milestone, it's the only megagate family that stores its configuration data in on-chip flash memory. The nonvolatile nature of the ProASIC technology enables designers to eliminate the external configuration memory and offer "instant" on capability since the configuration pattern doesn't have to be loaded at startup.
The largest family member, the APA1000, packs 1 million system gates, 198 kbits of dual ported embedded SRAM, and up to 712 I/O lines. Internally, the logic circuits can operate at clock rates as high as 350 MHz. External I/O operations can take place at 150 MHz. A PCI bus interface implemented in the configurable logic can operate at up to 50 MHz. A pair of PLLs are included on the chips for flexible timing and stable clock distribution. Also, the ProASIC Plus architecture continues to leverage the highly granular architecture of the previous ProASIC series, and it has a very fine granularity comparable to gate arrays.
Of course, Altera, Xilinx, and Actel also supply many lower-complexity FPGAs and complex PLDs to suit many system requirements. Several other companies have device families with up to about 580 kgates and some integrated system support features at the lower density levels. These makers include Atmel, Cypress Semiconductor, Lattice Semiconductor, and QuickLogic.
Of these, QuickLogic has the highest densities in the group. Its Eclipse series features up to 583,000 gates and 82 kbits of embedded SRAM. The company also has devices with the largest variety of pre-integrated functions--embedded MIPS processors, PCI interfaces, DSP support, SERDES ports, and Fibre Channel interfaces.
Unlike the SRAM or flash-based solutions produced by Altera, Xilinx, or Actel, QuickLogic's FPGAs are based on the company's one-time programmable antifuse configuration technology. The antifuses are formed in between metal layers above the silicon and thus do not require any silicon area. The FPGAs can then squeeze a lot of gates into very small chip areas.
ASIC vendors, noting the significant market advances FPGAs have made, have developed their own strategies to compete with FPGAs in both flexibility and fast turnaround times. Some of the players in this part of the market include Adaptive Silicon, AMI Semiconductor, Atmel, Chip Express, eASIC, Leopard Logic, Lightspeed Semiconductor, LSI Logic, and NEC. To see what these ASIC vendors are doing, check out "Fast-Turn Alternatives To FPGAs" at www.elecdesign.com.
The choices of logic architectures give designers plenty of options when selecting the best solution. And it won't stop here. Still higher-density FPGAs are on the drawing board, and they will deliver even higher levels of system integration and performance.