To set the filter corner frequency, the PSoC includes a digital SoCbloc configured as a timer. The filter output drives a 14-bit incremental ADC, which is built using a single analog SC SoCbloc and two digital SoCblocs. One of the digital SoCblocs functions as a sample-rate timer, while the other accumulates the lower 8 bits of the 14-bit conversion. The upper 6 bits are accumulated in the system software.
Pressure sensors often have offset voltages, which are compensated by driving an adjustable current into one of the bridge outputs. The current is adjusted by setting the duty cycle on the PWM that's configured using a single digital SoCbloc. Offset compensation values for the PWM are determined during a calibration routine. The on-chip temperature sensor is scanned directly into the ADC as an alternate input. Aside from pressure sensors, the only off-chip components used in this application are RC networks.
"The user modules define the internal setting within the SoCblocs, so that a specific function can be accomplished," John says. The company intends to expand this library as an on-going effort, adding even higher-level functions in the future. "The number of combinations are unlimited," he adds.
Employing the IDE software known as the PSoC Designer, a user can interconnect these higher-level user modules into a desired system by utilizing icons on the PC screen. "The capability to interconnect these user modules into a system is unique to this architecture," John notes. 'The user doesn't have to learn the minute details of the architecture and its interconnects. Instead, the designer can concentrate on higher-level functions and the end performance of the desired system. Both analog and digital user modules can be mixed and matched to obtain the end result."
The PSoC Designer comprises three subsystems. These include a device editor, an application editor, and a debugger. In the device editor mode, user modules are selected, pins are assigned, and register mappings are established (Fig. 4). The debugger provides hardware in-circuit emulation, thereby enabling the user to check breakpoints, trace memory, and observe traditional processor resources.
The CY8C25/26xxx is the first PSoC family. It's built around the 8-bit M8C microprocessor core. It includes a multiplier/accumulator and offers six to 44 general-purpose I/Os with a variety of programmable options. Multiple oscillator choices are available too for clocking the CPU, as well as analog and digital SoC-blocs. The amount of code and data memory depends on the device type. For code space, 4 to 16 kbytes of programmable flash are offered. For data, the SRAM density goes from 128 to 256 bytes.
The first four members of the CY8C25/26xxx family are made on the company's proprietary silicon-oxide/nitride-oxide silicon (SONOS) programmable nonvolatile process, which is integrated with Cypress' high-volume CMOS-based SRAM process. The procedure requires three additional masks to the standard process to provide nonvolatile memory and the flexibility of reconfiguration at the system level. The roadmap shows future PSoCs migrating to deep-submicron CMOS by the end of 2001.
Price & Availability
The first four PSoCs, the CY8C25122, CY826233, CY8C26443, and the CY8C26643, have been implemented in 0.35-µm CMOS. They will be sampling next month, with volume production to begin in the first quarter of next year. These devices will be available in 8-pin through 48-lead PDIPs, SOICs, and SSOPs. The C25122 comes in an 8-pin SOIC and PDIP, while the C26233 is an 18-pin version. Likewise, the C26443 and C26643 are encased in 28-lead and 48-lead housings, respectively. In 1000-piece quantities, the price range is $1.76 each for the low pin-count CY8C25122 to $3.53 each for the highest pin-count CY8C26643. The development kit costs $175. The C language compiler is $200.
Cypress MicroSystems, 12230 N.E. Woodinville Dr., Suite A, Woodinville, WA 98033; (425) 415-1523; Web site: www.cypressmicro.com.