SOI DESIGN KIT REQUIREMENTS
Cell layout and sizing are very different when using SOI technologies instead of bulk CMOS. The transistors' unique electrical features, whether fully or partially depleted, require different sizing to attain optimal performance. This ultimately affects design rules. As a result, direct migration of existing bulk CMOS libraries to a CMOS/SOI process yields poor performance as neither density nor speed is improved.
Unlike bulk CMOS, design kits for SOI aren't currently available. ASIC design requires a design kit composed of a library of standard cells (or gates), input/output cells (I/Os), and RAM and ROM compilers. Developing a library requires an established characterization methodology whereby all cells are simulated to determine their speed and power performance, while accounting for different load configurations. The methodology must also account for possible variations in process technology, power-supply voltage (±10%), and operating temperature (usually 0°C to 100°C).
For partially depleted SOI technologies, the methodology should also include propagation-delay variations caused by floating-body effects. The threshold voltage of such devices is affected by any external variations that change with time. This "history effect," named because the speed of a gate at a given time depends on its previous states, must also be accounted for in the design methodology.
Using a predictive SOI model is the best way to minimize the history effect's impact on partially depleted devices. The magnitude of the history effect depends on the gate type (e.g., inverter, NAND, NOR, XNOR, latch), but it's relatively small compared to all other possible variations (process, supply voltage, temperature). Even with this effect, SOI gates perform better than their bulk counterparts. They benefit from lower junction capacitance, lower threshold voltage, and lack of substrate effect, enabling optimal stacking of transistors. When the simulation shows that floating-body effects may affect the behavior of a critical circuit path, advanced design techniques are required.
SoCs clearly represent the future of electronic products. But integrating more and more functions into one chip will only be possible if power consumption is minimized. This means using all applicable design options (power-supply and clock management, implementing in hardware versus software). It also means reducing the power-supply voltage and, in turn, lowering the threshold voltage to maintain performance and increase leakage current.
With its low-threshold-voltage capability, SOI offers a solution to this dilemma. Fully depleted devices provide low sub-threshold swing and intrinsic capacitance. Partially depleted devices deliver low off-current with a high static VT and low dynamic VT (VT is reduced when the gate switches).
Because SOI substrates provide the high degree of isolation between functions that SoCs require, single-chip SOIs for high-performance devices such as wireless products are expected to become popular. As designers employ creative thinking to explore new ways to use SOI transistors, novel concepts like one-transistor DRAMs are emerging. The need for these kinds of new ideas will only increase as bulk CMOS approaches the physical limitations of its usefulness. High-resistivity SOI substrates are a real plus, while high-quality passive components can be implemented on substrates that exhibit low high-frequency loss.
Designers must understand that SOI isn't revolutionary, but rather part of the natural evolution of substrate materials. As with all aspects of semiconductor development, this evolution is essential to the future of SoCs and other advanced devices.
Designing ICs on SOI is rapidly becoming a mainstream technique, although it does require a thorough understanding of the SOI material to develop a design approach that fully exploits SOI's benefits. Figure 3 depicts a design flow optimized for SOI features. This is easiest to accomplish when designers work closely with SOI process and material providers.