Platform-Based Design
Building an SoC beginning with a standard set of IP is frequently called platform-based design. A typical IP collection with this approach is a processor core, a block of memory, and possibly a number of peripheral, interrupt, or DMA controllers.
The advantage of this approach is twofold. First, the base is well defined. Second, the base is typically well tested and doesn't require any verification other than what's necessary to test the linkage between it and additional IP.
CoWare's napkin-to-chip (N2C) product approach is designed to formalize the platform-based approach. It allows an SoC design to be based on an existing platform. This, in turn, can be tuned by changing high-end parameters. For instance, the amount of on-board memory used in the design could be altered.
CoWare has a number of domain-specific designs. For example, a digital-camera platform exists, as well as an xDSL platform. Obviously, each uses a different collection of peripherals, but even here there's a commonality that's typical with the core processor.
The platform-based approach has another advantage with N2C. The N2C interface synthesis support generates the IP to be incorporated in the SoC design, plus the software device drivers required to access this IP.
SoC designs have normally been done in-house using local hardware and software. But, Virtio Inc. is out to change that. This company's web site provides an interface for creating a system design model using Virtio's Magic-C as the HDL. This model can then be tested online. The simulation runs on servers located at Virtio's site. Though the model is functionally accurate, it isn't necessarily timing accurate.
Virtio's service is free. The Citrix-based client interface can be downloaded from the site. The sales model for the site is based on licensing third-party IP that will be available through the site.
Virtio recognizes the need to have in-house development tools, so it's marketing an intranet version of the system. It has the same flexibility, providing access to workstations on the intranet that typically operates at a much higher speed than an Internet connection. Furthermore, it addresses any potential security and secrecy issues.
While few organizations will be designing a large SoC using Virtio's site, it does open the door to smaller companies and startups. Those groups can develop small to medium-size SoCs or ASICs using the site. It minimizes up-front investment because there are no costs until IP is used to make a chip.
Major consulting firms, such as NEC Electronics Inc., are starting to utilize and support more robust co-design and co-verification tools. The fact that many are still building their suite of tools or evaluating third-party tools shows that this space is in flux.
For example, the company's ACE2 initiative began last year and won't be complete until 2002. NEC is working with third-party tools that will support the company's 800 series, MIPS' microprocessors, and SPX DSP cores. NEC understands the importance of both software and hardware simulation and has developed emulation boards for a number of third-party hardware emulation tools.
Co-design and co-verification tools are becoming invaluable as SoC complexity grows. Hopefully, these tools will be up to the job when designers need them.