The 100-kHz IF signals are filtered by simple passive RC low-pass filters and fed to programmable gain amplifiers controlled by the received-signal strength indicator circuits. The signals are then digitized by two delta-sigma oversampling analog-to-digital converters (ADCs) running at 13 MHz.
The digital outputs are sent to the Si4201 IF-to-baseband converter chip, where they're downconverted to baseband by digital mixers. Digital IIR channel filters provide most of the selectivity for the radio. Finally, the outputs are converted to analog by digital-to-analog converters (DACs) to provide compatibility with existing baseband interfaces. Demodulation of the GMSK data is performed in the baseband circuits. In the future, it's expected that the digital outputs from the ADCs in the Si4200 will go directly to the baseband chip set. That will perform the mixing and filtering, eliminating the need for the Si4201 and further reducing space, cost, and power consumption.
On the transmit side, the GMSK I and Q signals from the baseband circuits are upconverted to an IF signal in the 400-MHz range. The synthesizer chip provides the necessary IF local oscillator frequency. The transmit signal is generated by an on-chip VCO that's part of an offset PLL whose inputs are the 400-MHz data signals and a signal from a mixer. This offset PLL design acts like a bandpass filter centered on the carrier frequency. The bandwidth is approximately 1.5 MHz, which helps attenuate any noise or spurious signals that might exist in the reference in the transmit output. It eliminates the need for off-chip transmit SAW filters as well.
Low-Power Drivers
Low-power driver amplifiers supply sufficient output to operate the two off-chip higher power amplifiers, one for 900 MHz and the other for both 1800 and 1900 MHz.
The Si4133T synthesizer provides all of the signals for the transceiver. The primary input signal is the clock from an external temperature-compensated crystal oscillator (TCXO) at 13 or 26 MHz (Fig. 3).
The chip contains three independent PLLs. Two RF VCOs are designed for center frequencies of 1900 and 1350 MHz, and the IF VCO is designed for a center frequency of 825 MHz. The output range is adjustable over a ±5% range. All components including the loop filters are fully integrated.
"One of the greatest challenges of designing this chip was the VCOs," Tuttle says. To eliminate the need for laser trimming, a unique closed-loop feedback circuit with a self-tuning algorithm is used to center the VCO frequencies
Immediately after power-up or a change in the PLL division factor, the synthesizer's self-tuning circuit goes into operation. Its goal is to set each VCO as close to the desired frequency as possible before the analog tuning varactors take over. This self-tuning feature causes a bank of capacitors to be switched in or out to zero in on the desired frequency. The VCO uses the inductance of the bond leads as part of its resonant circuit.
The IF VCO uses an external inductor, while the RF VCOs use only the bond-wire inductance and a short pc-board trace. The self-tuning circuit leaves the VCO frequency within 1% of the desired frequency. The transmitter PLL also uses the self-tuning feature.
The PLL frequencies are set by loading the appropriate binary word into the PLL dividers. This is done via a 22-bit serial data word from the baseband processor. The settling time meets the GSM specifications and is more than sufficient to meet the requirements for class 12 GPRS.
Price & Availability
The complete chip set includes the Si4200 transceiver in a 32-pin microleadframe package (MLP), the Si4201 baseband interface in a 20-pin MLP, and the Si4133T in a 28-pin MLP. Total cost for the chip set is $8.62 in quantities of 10,000. Samples are available now. Volume production will be available in the second quarter.
Silicon Laboratories Inc., 4635 Boston Lane, Austin, TX 78735; (512) 416-8500; fax (512) 416-9669; www.silabs.com.