A glance at the block diagram of the PI7C7100 indicates the important configuration registers A and B (Fig. 2). These two registers provide a multifunction or dual-function device with space to accommodate the two secondary PCI buses.
The transaction queue and buffers have a rather deep FIFO architecture, with 256 bytes on the writes and 128 bytes on the reads. There are two sets of each to enable concurrent operation. This is useful for cases in which a device on secondary bus two wants to talk to a device on secondary bus one. Data goes through this FIFO to accommodate any device latencies.
Direct Connection Between Buses
Communication between the two secondary buses exists as a direct connection and can be compared to the operation of a switch fabric. The chip provides the equivalent of a point-to-point connection. In between are the FIFOs, which act as buffers and ensure that a link is established between the secondary one and secondary two buses.
The chip supports up to eight masters per secondary bus for a total of 16 masters. If there are two devices on secondary bus two, they can easily talk to each other. If the devices are on separate buses, a direct link is established. Therefore, it's as if both devices are on the same secondary bus.
The PI7C7100 is an 0.35-µm CMOS device that is fully compliant with the 32-bit, 33-MHz implementation of the PCI Local Bus Specification, Revision 2.1. It supports synchronous bus transactions between devices on the primary 33-MHz bus and the secondary buses operating at 33 MHz. The primary and secondary buses can also operate in the concurrent mode, which increases system performance. Concurrent bus operation offloads and isolates unnecessary traffic from the primary bus. In addition, all three ports meet the PCI-to-PCI Bridge Architecture Specification, Revision 1.0.
As for software support, most BIOSs can recognize and properly configure a standard PCI-to-PCI bridge. As this device adheres to the PCI bridge architecture specification, most BIOSs will know how to program it. When a BIOS does enumeration, it will see this device as two bridges and automatically configure it as if it were two separate PCI-to-PCI bridges. If this were to happen, the device would behave as two separate bridges. Everything would function properly, except for the overhead of traffic on the primary bus.
For the device to work as designed, a software driver is needed to program the registers in the chip. This driver sets the addresses from one expansion board to the other on the two secondary ports. It also establishes the direct link mentioned earlier. In other words, a special driver is required to take advantage of this feature.
For telecom, video-server, and similar applications, 33 MHz and 32 bits are presumed sufficient. But the trend is to aggregate all these channels into a single high-performance one. This would require higher-performance bridges. Pericom's plans call for a three-port bridge device that contains a 66-MHz, 64-bit primary bus as well as 66-MHz, 64-bit secondary buses. The company has already defined this and is working on releasing it in the fourth quarter.
Price & Availability
The PI7C7100 is available now in a 256-pin plastic BGA package. Pricing is $30 each in 1000-unit quantities.
Pericom Semiconductor Corp., 2380 Bering Dr., San Jose, CA 95131; (800) 435-2336; nolimits@pericom.com; Internet: www.pericom.com.