The transmitter's I2C master functional block hosts the communication with the key PROM (Fig. 3). The 40-bit AKSV residing in the transmitter PROM is fed via the block and stream cipher to the CP controller. From there, it's sent to the graphic controller and the HDCP receiver for authentication purposes. The keys themselves never come into the clear, remaining protected and inaccessible.
The I2C slave in the transmitter, which carries bidirectional control signals, interconnects with the graphics controller transmitter and the HDCP LCD monitor controller. Authentication between the receiver and the host occurs through this link.
Arriving data enable (DE), data, and clock signals enter the data-capture circuit. Then they are fed to the XOR mask. There, the cipher is added to the data, thereby encrypting it. The encoder takes the video data of 8 bits of color information per pixel, or a total of 24 bits of information—red, green, and blue—and converts it from an 8- to a 10-bit format by adding two bits of encoding information to the video data. Finally, the data is serialized, becoming three data channels (0, 1, and 2) and one clock channel (C).
Pin-Compatible With Earlier Version
The SiI 168 PanelLink HDCP transmitter is pin-compatible with the earlier SiI 164 transmitter. It provides 165-MHz operation with or without the encryption running. Functions such as key downloading, authentication, frame, and session key calculation are automatic and remain transparent to the user. Dual-link support can be realized by adding a second SiI 168.
A deskewing option lets designers vary the clock-to-data timing. The SiI 168 supports dual-edge/single-clock or single-edge/dual-clock clocking in the 12-bit mode. In the 24-bit mode, it supports single- or dual-edge clocking. Parallel data can be latched on either the positive or negative edge of the clock signal.
The transmitter has a programmable interface to provide power-management control. Chip configuration/programmability, identification information, and 8 bits of user-configuration data in the 12-bit mode are supplied as well.
This setup is hot-pluggable, too. If the transmitter or receiver is unplugged and then reconnected, there is no need to manually tell the system to reissue an authentication. The process is initiated automatically. Also, the procedure is transparent to the user.
The SiI 168 HDCP exhibits high interpair skew tolerance of up to one input clock cycle—6 ns at 165 MHz. The transmitter provides cable-distance support via adjustable low-voltage-swing signaling for long-distance support, as well as dc-balanced signals for direct coupling to modules that are ready for fiber optics.
The companion SiI 861 DVI HDCP LCD monitor controller includes an integrated PanelLink receiver, comprising the deserializer and the decoder, with a 165-MHz scalable bandwidth. It can operate with PanelLink transmitters—both with and without HDCP. Like the transmitter, it supports 165-MHz operation while the decryption is running.
The 40-bit BKSV residing in the receiving PROM is fed via the I2C master through the block and stream cipher to the CP controller (Fig. 4). From there, it's sent to the transmitter for authentication purposes and to the XOR mask for decryption of the data arriving at the receiver. Still, the key itself never comes into the clear.
The I2C slave, which carries bidirectional control signals, interconnects the LCD monitor controller with the transmitter and the graphics controller. Authentication between the receiver and the host occurs through this link. Data arriving on channels 0, 1, 2, and C enters the deserializer and is decoded. It is then fed to the XOR mask and to the pixel precision-image-processing circuit. Next, it's sent to data formatting, which recreates the data and clock signals that are ultimately fed to the LCD panel.
The SiI 861 LCD monitor controller provides flexible and efficient power management, full-featured image processing and scaling, dithering, gamma tuning, and on-screen display. Functions such as key downloading, authentication, frame, and session key calculation are automatic and transparent to the user. Like the transmitter, the LCD monitor's input exhibits an interpair skew tolerance of up to one input clock cycle—6 ns at 165 MHz. The SiI 861 HDCP LCD monitor controller is designed for 3.3-V core operation. A power-down mode is included.
Price & Availability
Sample quantities of the SiI 168 DVI HDCP PanelLink transmitter will be available this quarter. Volume quantities are slated to begin shipping in the third quarter. The price is less than $5.00 each in high volumes. Sample quantities of the SiI 861 DVI HDCP PanelLink LCD monitor controller also will be available this quarter. Volume quantities will begin shipping in the third quarter. Its price is less than $15.00 each in high volumes. The SiI 168 will be shipped in a low-cost, industry-standard 64-pin TQFP, whereas the SiI 861 will be shipped in a 208-pin TQFP.
Silicon Image Inc.,1060 E. Arques Ave., Sunnyvale, CA 94086; (408) 616-4000; fax (408) 830-9530; www.siimage.com.