Sometimes, designers need more compute power. In that case, PowerPlug accelerators can be added to the architecture by tapping into the data-bus switches. The accelerators can be linked to the software via the CLIW commands, which the user must construct.
The Carmel 20XX core generates the memory addresses, control signals, and wait states. It also provides the PowerPlug accelerator operation codes and operands while writing back the results to the memory. PowerPlug-enabled development tools recognize PowerPlug-extended CLIW instructions. The accelerators are fully supported during debug and emulation, including the ability to view PowerPlug-specific internal registers.
The accelerators decode their own instructions, control their own registers, and perform the desired datapath function. The CLIW commands provide flexible software control of the PowerPlugs. Since the accelerators are modular and interruptible, the DSP designer can mix and match the PowerPlug accelerators and then dynamically select them at every instruction. The accelerators also support memory wait states.
Able to control up to four PowerPlug accelerators simultaneously, the CLIW operations employ 16-bit instructions for each PowerPlug. Those instruction opcodes are coded inside the CLIW word and passed to the appropriate PowerPlug unit along with the operands. Opcodes can optionally be extended to 32 bits for use with very sophisticated PowerPlug functions.
CLIW instructions are 144 bits wide. They're structured as a 48-bit instruction word that's stored in program memory, and a 96-bit instruction word (six 16-bit instructions) stored in the CLIW active memory (an SRAM block). The RAM can hold up to 2048 CLIW instructions. An 11-bit field in the 48-bit instruction word is used to index the CLIW memory and serve as a lookup pointer to fetch the correct 96-bit custom instruction, which is divided into six parallel subinstructions.
The first four subinstructions apply to the basic Carmel 10XX/20XX common architecture for the two ALUs and two MACs. PowerPlug instructions can be substituted for any or all of these four original instructions. The remaining two instruction slots usually hold memory-access instructions.
The Carmel core uses 24-bit instructions. Those instructions can be extended to 48 bits to get a wider selection of operands that have larger immediate operand fields and direct operand references. In a single cycle, the core can execute one standard 24-bit instruction, two standard 24-bit instructions, or one standard 48-bit instruction. The CLIW architecture extends the "traditional" DSP instructions by an additional 96 bits.
The core supports conditional execution through a predication mechanism that avoids branch penalties and also avoids the use of fast context switching. It utilizes a register-bank exchange instruction and a conditional-execution load instruction. Hardware looping support is available in the DSP core to allow zero-overhead loops, nested up to four levels. Back Trace instructions that accelerate functions such as Viterbi decoding are included as well.
ALU instructions support double-precision operations. Also, there are special instructions for square, divide, minimum/maximum, block floating point, logical and arithmetic shifts, bit manipulation, fractional and integer arithmetic, and other special operations. These unique operations include limiting, saturation, nearest and convergent rounding modes, and special instructions for efficient C-compiler support.
Price and Availability
The Carmel 20XX core is immediately available. The license fee for the core and the PowerPlugs depends on volume and other factors. To discuss license fees, contact Shaul Berger.
Infineon Technology Inc., 1730 N. First St., San Jose, CA 95112; (800) 777-4363; www.infineon.com.