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As the system-on-a-chip (SoC) era marches forward, there's a pressing need to embed large amounts of memory onto a logic chip and make the resulting technology as flexible and cost-effective as possible. SRAMs don't require the overhead of refresh management, so there are always going to be small, distributed SRAM memory blocks on-chip.
Yet real estate problems crop up with SRAM. This is where the relatively new technology known as 1-Transistor Random Access Memory (1TRAM) can be implemented to replace sizable SRAM blocks. The 1TRAM is a special DRAM, and its memory cell is based on charge storage in a capacitor. Over time, charge leaks out of the storage node. The charge has to be restored periodically for the memory to operate properly. The designed-in time period of charge restore is called refresh time, or TREF.
Because 1TRAM has no single-set refresh spec associated with a process, designers must consider several factors when evaluating TREF. This article discusses those factors and explains several techniques that can improve the refresh characteristic while still keeping minimum cell size.
One key area for 1TRAM application is digital signal processing. DSP requires SRAM-style memory. Operating speed and memory density with 1TRAM are usually enough for most DSP applications.
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