Use Embedded RISC Processing To Boost Router Power

Select and shift left (SELSL) and select and shift right (SELSR), used to build a word of data from multiple sources of data, are another pair of CW4011 instructions with strong value for router applications. An example application for the SELSR and SELSL instructions would be the protocol conversion by a router of an ATM header to a frame relay header.

One example is to modify the IP header or tag field in a routing application. Much of the conversion can be accomplished by using fields of the ATM header to index entries in a series of tables. These pieces are isolated by using the SELSR/SELSL instructions combined with the base address of the table to provide access to the translation value stored in the table. The translation values from multiple tables are then combined using the SELSR and SELSL instructions to build up the new header.

This example displays not only the use of those instructions for building a data word out of multiple components, but also deconstructing fields in a header or data word to quickly index to the action or value required by that field. A simple operation without these special instructions could require two or three additional instructions to implement.

The need for extra features and faster data rates is dramatically increasing the performance demands on the processors in router architectures. Embedded RISC processors can help to address this increasing performance gap in three ways: high and increasingly higher instruction execution speeds that are the trademark of RISC architectures, semi-custom instructions provided for typical router applications including table accesses and buffer management, and fully customized add-on hardware such as the packet header cache example discussed in this article. RISC technology can be used to implement these high-throughput designs while maintaining the flexibility of a processor-based implementation.

Select and shift left (SELSL) and select and shift right (SELSR), used to build a word of data from multiple sources of data, are another pair of CW4011 instructions with strong value for router applications. An example application for the SELSR and SELSL instructions would be the protocol conversion by a router of an ATM header to a frame relay header.

One example is to modify the IP header or tag field in a routing application. Much of the conversion can be accomplished by using fields of the ATM header to index entries in a series of tables. These pieces are isolated by using the SELSR/SELSL instructions combined with the base address of the table to provide access to the translation value stored in the table. The translation values from multiple tables are then combined using the SELSR and SELSL instructions to build up the new header.

This example displays not only the use of those instructions for building a data word out of multiple components, but also deconstructing fields in a header or data word to quickly index to the action or value required by that field. A simple operation without these special instructions could require two or three additional instructions to implement.

The need for extra features and faster data rates is dramatically increasing the performance demands on the processors in router architectures. Embedded RISC processors can help to address this increasing performance gap in three ways: high and increasingly higher instruction execution speeds that are the trademark of RISC architectures, semi-custom instructions provided for typical router applications including table accesses and buffer management, and fully customized add-on hardware such as the packet header cache example discussed in this article. RISC technology can be used to implement these high-throughput designs while maintaining the flexibility of a processor-based implementation.