As the cost to create ASICs continues to climb, a board
design featuring multiple, more generic ICs becomes
attractive. But arriving at a standardized, high-speed
board interconnect has proved difficult.
The XMOS Link, as implemented in the XS1 family of programmable
devices, can be used as a standard board interconnect
for seamless connection between multiple devices to address the
problem. In particular, an XMOS Link can be readily implemented
in an off-the-shelf microcontroller.
XS1 ARCHITECTURE
The XMOS chip architecture combines a number of processing
cores (“XCores”), each with its own memory and I/O. The cores
run at 400 MHz/MIPS, and they directly support communication,
ports, and concurrent processing through multiple threads.
C is supported, as well as “XC,” a C-like language with added
capabilities for inter-thread communication and I/O. An on-chip
switch supports communication between processors, and external
XMOS Links are used to communicate with other chips.
XMOS Links enable communication between all processors in
the system by allowing streams of data and control information
to be transmitted with low latency across the network. Streams
are circuit switched, but can be set up and terminated easily,
allowing them to be used to create a packet-switching network.
From an application perspective, the architecture provides a
channel end resource, with communication occurring between
two channel ends. The programming model is independent of the
destination channel end’s location, which may be on the same
processor, on different cores within the same device, or on separate
devices.
PHYSICAL LAYER
XMOS Link communication uses a non-return-to-zero transition-
based scheme. Transmission involves a stream of tokens,
each consisting of several symbols that may encode one or more
bits depending on link mode. A token contains 8 bits and a control
token flag. There are two modes of link operation.
The slower, serial mode uses two data wires, “0” and “1,”
in each direction—four wires in total. A single transition corresponds
to a single bit of information. The level of the wires is
irrelevant; a transition should never occur on both wires simultaneously.
For each token transmitted, 10 transitions (symbols)
are sent. The first eight are data, followed by a control token flag,
and lastly an even parity bit.
The faster link mode uses five data wires in each direction,
with 10 wires in total. There are four data wires and an “escape”
wire. Four transitions (symbols) are required to transmit a token,
with a transition on the escape wire signaling a control token. A
token transmitted in fast mode may result in zero, two, or four
wires being high. To return to zero, an optional return-to-zero
NOP token can be sent, resulting in all five wires being low.
A link is clocked from the System Switch, which runs by
default at 400 MHz. The speed of a link can be adjusted by
changing the number of clock cycles between tokens and the
number of clock cycles between symbols. The minimum value
for each field is 2, and the maximum is 2049. This results in a
data throughput of 156 kbits/s to 160 Mbits/s for the serial link
and 390 kbits/s to 400 Mbits/s for the fast link. The System
Switch itself can also have its speed dynamically lowered using
an 8-bit divider.
XMOS Link wires are multiplexed with standard generalpurpose
I/O pins on XS1 devices. Software can enable the links,
which will then take priority on the multiplex.
LINK LAYER
The link uses a full-duplex point-to-point connection with
a credit scheme for synchronizing communication. Each link
includes a credit counter
and a credits-issued counter,
with three reserved
control tokens used to
transmit credits. To initialize
the link, software
must first enable it, then
request a HELLO token
to be sent. This will reset the internal credit counter. The counterpart
link will reset its credits-issued counter
and issue credits.
Whenever a link sends a token, it will
decrement its credit counter. When a link
is aware its counterpart is low on credits
and is ready to receive more data, it will
transmit credits as a control token. This
method allows a link to control the transmission
of tokens, making it possible to
throttle down the data rate if required.
SWITCH LAYER
The XMOS Link relies on a unique identifier
being assigned to every device in the
system. This ID is sometimes referred to
as “node,” “core,” or “processor” ID. Upon
transmission of a data stream, a packet
header is first sent. This header includes
the ID of the packet’s destination node,
which may be any number of hops away.
Assuming a path can be found through the
network, this header will establish a connection
until the end of the packet.
Routing tables, stored in every node in
the system, determine a route. When the
System Switch of a node receives a data
stream, it compares the destination processor
ID with its own. If it matches, the
packet has reached its destination, and all
subsequent traffic is then routed into the
core itself.
In case of a non-match, the switch must
choose an outgoing link for the packet to
travel down. It does this by considering
the position of the first non-matching bit.
This is then passed into the routing table
and used to look up the dimension (direction)
to route the stream. Every direction
is assigned one XMOS Link or more. This
way, systems can be constructed using
most common network topologies: pipelines,
grids, stars, and trees, for example.
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