Adaptive Computing Overcomes Barriers To 3G Wireless Comm

Differing Design Flows: The design flow between a DSP and an adaptive-computing machine begins to differ at the 16-bit fixed-point conversion. At this stage, adaptive computing starts to pay major design benefits. At the 16-bit fixed-point conversion stage, bit accuracy becomes a moot point because adaptive computing doesn't only offer a fixed 16-bit machine that can simulate 32-bit instructions. On the contrary, adaptive computing is a variable-precision machine that reduces the limitations on bit widths. A design doesn't have to be 16 bits. It can be 1, 8, 16, 24, or 32 bits or larger, offering considerable flexibility over the highly restrictive DSP 16-bit fixed-point conversion.

If certain operations require higher precision, that particular information will be specified in the high-level language (HLL), and no performance penalty is associated with ordering the higher bit precision. Also, the cost of going from 16 to 32 bits is much lower than with a DSP. For example, with an ACM, structures handling either 16- or 32-bit multiplications can be created. Each structure is equally efficient with virtually no design penalties. The program performs at the same speed whether it's a 32- or 16-bit execution.

The difference is that more computational resources are used in the ACM, but not more time. This form of conversion brings smoother simulation. Even if errors occur in the conversion process, simulation remains simpler than with a DSP because increasing precision doesn't generally make an impact on time necessary to execute an algorithm. By using adaptive computing at the resource-mapping stage of a design, the designer has ample re-sources and subsequent performance as these resources operate simultaneously and asynchronously.

Inherently, a DSP executes one in-struction at a time and a series of sequential instructions to perform a given function. On the other hand, adaptive computing performs the same function considerably faster by executing many groups of HLL operations as a single algorithmic block.

Further, the interconnect structure between resources on an adaptive-computing chip is nonblocking, as compared to a DSP where bus contention issues are a major performance concern. This means that bandwidth is available whenever two resources (nodes) must connect, thereby contributing to higher performance.