As serial-data standards go from fast to very fast, designers must devote a greater amount of time to the analog features of those high-speed signals. It’s no longer enough to remain in the digital domain with ones and zeros. To find and correct conditions that lead to potential problems—and thereby prevent those problems from showing up in the field—designers must check the parametric realm of their designs. Signal integrity (SI) engineers have to mitigate or eliminate the effects of timing jitter on system performance. The following discussion offers a simple and practical procedure for characterizing high-speed serial data links at 1Gbps and beyond.
The characterization of a high-speed serial link depends on the ability of the SI engineer to find, understand, and solve serious jitter problems. In this discussion, we assume that the clock and data recovery (CDR) block of the PHY (physical layer) or SERDES (serializer-deserializer) device complies with the standards applicable to that device. In a serial communication system, the CDR recovers the clock signal from the data stream. Therefore, a key operation is to extract data from the serial data stream and synchronize it with the data-transmitter clock.
The transmitter always contributes some jitter to the recovered clock, but let’s assume that contribution to be minimal. For the purpose of simplification, we’ll assume any jitter seen on the recovered clock to have been coupled either onto the link in the cable (as EMI) or within the PCB (as cross-talk).
Jitter transfer, jitter tolerance, and jitter generation are important measures, but they apply more to PHY and SERDES devices than to the testing of system channels. Imagine the devices used in our design meet all device-level compliance testing, and we can focus on the complete system as we find a way to reliably capture serial data at the receiver. We’ll look at system-channel characterization rather than device characterization. Such a channel consists of the transmitter PHY, FR4 (PCB material), connector, shielded cable, connector, FR4, and receiver PHY (Figure 1).
The embedded telecomm card, a mixed-signal board used to collect many of the measurements in this article, is part of a “radio unit.” The radio unit connects to the base station via a Common Public Radio Interface (CPRI), a new standard for communications between a base station and a radio unit. One physical layer in the CPRI includes the radio data (IQ data) as well as management, control, and synchronization information. For the application described in this article, the CPRI was specified to run on a serial link at 1.2288Gbps. This serial link was then characterized and measured to illustrate the jitter tests.
Jitter–Understanding Its Make-Up
The most important steps, therefore, in achieving the performance specified for a high-speed serial-communications interface include understanding jitter, finding its causes, and eliminating some of its effects. Although this article is not a tutorial on the topic of jitter, it’s hard to talk about testing a serial communication link without saying at least a word or two about jitter. Accordingly, the discussion in this section is directed to those who are new to the subject.
Jitter is defined as the variation of a signal edge from its ideal position in time. More specifically, jitter is the misalignment of the significant edges of a digital signal from their ideal positions in time (Figure 2). Jitter can also be viewed as an unwanted phase modulation of the digital signal. The SI engineer must understand: a receiver that meets the serial-link data rate but does not meet its jitter specification may not operate reliably. Jitter characterization is therefore essential in guaranteeing an acceptable bit error rate (BER) for the system. Jitter can affect timing margins, synchronization, and cause a long list of other problems.
Viewed as deviations of output transitions from their ideal positions, jitter is an important performance measure for both the clock and data signals of a serial link. The continuous incremental addition of jitter leads eventually to data errors. Remember, any time-domain measurement taken on a hardware system is only as good as the sampling signal used to acquire it.
Today’s serial-communication systems have opted to embed clock information in the data stream rather than using an external trigger signal at the receiver. The clock must therefore be recovered from the received bit stream itself. This function, known as Clock and Data Recovery (CDR), is shown in the block diagram for a typical SERDES receiver (Figure 3). If, however, the incoming signal has more than a certain amount of jitter or phase noise, the recovered clock cannot stay accurately aligned with the data. Misalignment causes an inaccurate placement of individual data points in time.