As the systems that support the Internet and Metropolitan-Area Networks (MANs) in both the edge and core are called on to handle more packet traffic, existing line card designs are running out of steam. The level of integration available today typically allows designers to implement an OC-192 (10-Gbit/s) channel per line card. But as bandwidth needs grow from gigabits per second to terabits per second, system racks won't be able to power or support the large number of line cards necessary.
To solve the board space and power challenges and provide a scalable solution, designers at Teradiant Networks concentrated on integrating many line card functions into a chip set that can reduce line card cost and power consumption by two-thirds. The TeraPacket chip set provides scalable performance, allowing designers to implement line cards with 10-, 20-, or 40-Gbit/s aggregate throughputs. The chip set performs both packet processing and traffic management functions along with full quality-of-service (QoS) management at line rates.
The QoS features support packet classification to determine the kind of flow and decide which priority queue to move the packet into. Policers/markers enforce the service provider throughput agreements. Hierarchical queues provide an extensive set of queues to meet any service provider priority needs. According to industry-standard algorithms, schedulers determine which queue to service, based on priority. Lastly, traffic shapers help throttle the flow through an individual queue. This lets the chip set manage and maintain the right amount of traffic over the network.
The two chips, used in various combinations, along with the appropriate memory buffers and network interfaces permit designers to implement line cards that pack up to four OC-192 ports, four 10-Gbit Ethernet ports, or 16 OC-48 ports. Thus, systems such as Internet routers, multiservice switches, hybrid TDM/data switches, and MAN switches are found both in the network edge and core, and storage-area-network servers can move more data at a lower cost and less power per channel.
Additionally, the high level of integration provided by the chip set keeps board space to a minimum. For example, at the high-end of the performance curve, four 10-Gbit/s channels can squeeze onto one line card using the TeraPacket chip set. In contrast, existing chip solutions might typically permit designers to implement just a single 10-Gbit/s port on a line card before exceeding space or power allotments.
To achieve the high level of integration, designers at Teradiant developed a flexible, fully configurable super-pipelined architecture. The company is currently preparing over 20 patent applications to cover many architectural innovations. Two functions divide the chip set—the multiservice packet engine and the multiservice traffic manager. Each chip is actually available in three slightly different versions for designers implementing 10-, 20-, or 40-Gbit/s subsystems.
In a 10-Gbit/s full-duplex system, the line card would include one TN100 Packet Engine and one TN101 Traffic Manager. A 20-Gbit/s solution would also require only one packet engine and one traffic manager. However, such a system would employ the TN200 and TN201, which have expanded I/O and memory interfaces to handle the higher data traffic. No other external memory is needed, except a small packet memory. This reduces system memory cost compared to previous approaches. In a 40-Gbit/s full-duplex implementation, two copies of the TN400 Packet Engine and two copies of the TN401 Traffic Manager chips are used (Fig. 1). Here again, the bus interfaces and some internal operating modes have been modified to accommodate the higher data traffic.
The chips are designed to handle all well-established communication protocols, including IPv4, IPv6, ATM, frame relay, point-to-point protocol (PPP), Ethernet, multiprotocol layer switching (MPLS), and the MPLS Martini draft. In a departure from the more traditional software-based network processors that use internal microcode to control operation, the TeraPacket chip set employs a hardwired yet configurable architecture. The hardwired (state machine) approach enables the chips to execute their operations much faster than a microcode-based solution. At the same time, designers included plenty of user-configurable internal registers and tables to set the various operating parameters for the multiple communications protocols and standards.