DESIGN VIEW is the summary of the complete DESIGN SOLUTION contributed article, which begins on Page 2.
The relentless rise in network traffic rates and the ongoing shift from circuit-switched to packet-based architectures promises to bring a variety of new challenges to communications-systems design. Many of these systems will reach success only if the design team can maximize data-flow efficiency by building highly efficient and cost-effective subsystems for data segregation, data prioritization, and bandwidth aggregation.
So it's no surprise that memory subsystem design has become a full-time job for system architects and designers of networks, cellular basestations, and data-acquisition systems. In the process, they have seen a growing percentage of their design resources and development time spent on the arduous task of building highly specialized memory subsystems for bandwidth aggregation, data segregation, and data prioritization.
Complicating this task has been the rapidly changing mix of data types running across current networks. While most data remains sequential in nature, the rising use of audio and video has placed new time demands on the transfer process. As a result, there's a new premium on subsystems that can prioritize data as it flows through the system and provide the data-management functions needed to meet the demand.
This article takes a look at four different options when building a data-flow-control subsystem: use of off-the-shelf specialty memories a custom home-grown solution using an FPGA or ASIC with integrated memory devices a custom home-grown approach based on external memory and a smaller, more affordable FPGA or the use of flow-control-management (FCM) ICs. FCM devices are discussed in depth, as the author concludes that these chips may provide the most attractive combination of performance and functionality at low cost.
Full article begins on Page 2
DESIGN VIEW is the summary of the complete DESIGN SOLUTION contributed article, which begins on Page 2.
The relentless rise in network traffic rates and the ongoing shift from circuit-switched to packet-based architectures promises to bring a variety of new challenges to communications-systems design. Many of these systems will reach success only if the design team can maximize data-flow efficiency by building highly efficient and cost-effective subsystems for data segregation, data prioritization, and bandwidth aggregation.
So it's no surprise that memory subsystem design has become a full-time job for system architects and designers of networks, cellular basestations, and data-acquisition systems. In the process, they have seen a growing percentage of their design resources and development time spent on the arduous task of building highly specialized memory subsystems for bandwidth aggregation, data segregation, and data prioritization.
Complicating this task has been the rapidly changing mix of data types running across current networks. While most data remains sequential in nature, the rising use of audio and video has placed new time demands on the transfer process. As a result, there's a new premium on subsystems that can prioritize data as it flows through the system and provide the data-management functions needed to meet the demand.
This article takes a look at four different options when building a data-flow-control subsystem: use of off-the-shelf specialty memories a custom home-grown solution using an FPGA or ASIC with integrated memory devices a custom home-grown approach based on external memory and a smaller, more affordable FPGA or the use of flow-control-management (FCM) ICs. FCM devices are discussed in depth, as the author concludes that these chips may provide the most attractive combination of performance and functionality at low cost.
Full article begins on Page 2