Evaluate Power-Supply Noise Rejection In Low-Jitter PLL Clock Generators

Clock generators that integrate phase-locked loops (PLLs) find many homes in network equipment. Their main function is either to generate high-precision and low-jitter reference clocks, or maintain a synchronized network operation. Most clock oscillators provide their jitter or phase-noise specification using an ideal, clean power supply. In a practical system environment, the power supply can suffer from interference due to on-board switching supplies or noisy digital ASICs. To achieve the best performance in a system design, it’s important to understand the effects of such interference.

PSNR Characteristics of PLL Clock Generators
Figure 1 shows a typical PLL clock generator. Since the output driver can have very different power-supply noise rejection (PSNR) performance for different types of logic interfaces, the following analysis will focus on the supply noise impact to the PLL itself.

Figure 2 shows the PLL phase model assuming that the power-supply noise V_N is injected into the PLL/VCO, and the divide ratios M and N are set to 1 (Fig. 2).

The PLL closed-loop transfer function from V_N(s) to φ_O(s) is given by

For a typical second-order PLL,

Here, Ω_3dB is the PLL 3-dB bandwidth, Ω_Z is the PLL zero frequency, and Ω_Z3dB.

Equation 3 demonstrates that, in a PLL clock generator, the power-supply noise is rejected by 20 dB/s when the supply interference frequency is greater than the PLL 3-dB bandwidth. For power-supply interference frequencies between Ω_Z and Ω_3dB, the output clock phase varies with the power-supply interference amplitude as:

As an example, Figure 3 shows the PSNR characteristics of a PLL for two different settings of the PLL’s 3-dB bandwidth.

Conversion of Power Spectrum Spurs to DJ
When a single-tone sinusoidal signal, f_M, is applied to the power supply of a PLL, it produces a narrow-band phase modulation at the clock output, which can be generally described using Fourier series representation:

Here, β is the modulation index representing the maximum phase deviation. For a small index modulation (β

Here, n = 0 represents the carrier itself. When n = ±1, the phase-modulated signal is given by:

Equation 8 demonstrates that, when measuring the double sideband power spectrum S_V(f), if varible x represents the level difference between the carrier at f_O and the fundamental sideband tone at f_m, then:

where x = decibels relative to the carrier (dBc).

Since β is the maximum phase deviation in radians, the peak-to-peak deterministic jitter (DJ) caused by this small index phase modulation can be derived:

where DJ = picoseconds peak-to-peak (ps p-p).

The above analysis assumes that no amplitude modulation is contributing to the tone at f_M. In reality, both amplitude and phase modulation can be generated, reducing the accuracy of this approach.