With speeds of up to several hundred megabits/s, fiber to the
home (FTTH) would be the best broadband service available—if it weren't
so expensive. Freescale Semiconductor
takes a shot at reducing some of those
costs with its MSC7120 chip set.
According to the company, the average
U.S. home is going to need as much as 40
Mbits/s to support one HDTV channel, two
MPEG2 digital TV (DTV) channels, Internet
access, Voice over Internet Protocol (VoIP)
phones, gaming, and other services by
2009. And today's infrastructure just can't
handle those demands.
DSL only delivers a fraction of that
bandwidth, and we're still a few years
away from VDSL2. Cable TV comes closer
with its DOCSIS 3.0 systems, where channel bonding can boost downstream rates
well into the desired range—for a price.
Also, hybrid fiber/VDSL2 systems are now
showing up as AT&T rolls out its U-verse
Internet Protocol TV (IPTV).
FTTH installation can cost as much as
$1800 per customer in the U.S. Yet gigabit
passive optical networks (GPONs) are
reducing some of these costs. Japan and
Korea have adopted the Ethernet PON
standard, which delivers 1 Gbit/s on the
downstream and upstream links. Verizon
is installing FTTH with its FiOS system as
well. As fiber prices continue to drop, more
FTTH will occur.
Freescale's MSC7120 system-on-a-chip
(SoC) targets customer premises equipment (CPE) like set-top boxes, which are
called optical network terminals (ONTs) in the jargon of PONs. It supports data, voice,
and video. It also complies with the ITU's G.984 GPON standard. In fact, it's the latest variation of the standard that started
with APON and BPON.
The GPON standard is capable of 2.4
Gbits/s downstream and 1.2 Mbits/s
upstream in a PON that can serve up to 64
subscribers on a single fiber. The entirely
passive network consists only of the fiber
and a number of passive splitters/combiners. GPON's very low cost and near total
lack of need for maintenance removes a
huge cost from the deployment equation.
The MSC7120 incorporates a
Freescale Power Architecture e300 core
for control path operation, a dedicated
packet engine for the data path, and a
StarCoreSC1400 DSP core for VoIP processing. The I/O includes 48 general-purpose I/O pins, UART, SPI, I2C, and
timers. Other interfaces include JTAG as
well as DDR and DDR2 memory controller interfaces. Its dual 10/100/1000
Ethernet media-access controllers
(MACs) support RGMII.
The PON subsystem complies with the
ITU-T G.984 GPON standard. It integrates
the TC/MAC function, the clock and data
recovery (CDR), and the interface to the
optical transceiver. Forward error correction (FEC) with AES is included. The housing is a 456-pin thermally enhanced
PBGA package. Samples are available
now, as are reference designs and an
evaluation board (). Check
with Freescale for pricing.
Freescale Semiconductor
www.freescale.com/PON