Key Design Aspects Of CMOS Image Sensors Revealed

Lowering current consumption on chopper-type comparators
In recent years, chopper-type comparators have become common in the ADC AFE, especially for high-resolution CISs that also require high speed and low power consumption. The basic structure of a chopper-type comparator consists of a multiplexer, an autozeroing-two-stage inverter/amplifier, and coupling capacitors (Fig. 3a).

The multiplexer switches the input to the first node of the first coupling capacitor (C1) between a reference voltage V_REF and the photo signal V_IN. A second coupling capacitor (C2) transfers the data from the first inverter/amplifier stage to the next. Autozeroing, or self-offset cancellation function, is achieved by closing both transfer gates (TG1 and TG2). This forces the inverter/amplifier inputs to the same voltage as their outputs.

Only one clock, CLK, and its complement, CLK~, are needed to control the operation of this type of comparator. When CLK is HIGH, V_REF is applied on the first node of the first coupling capacitor. At the same time, TG1 and TG2 are closed for autozeroing. When the CLK signal goes LOW, V_IN– V\[_REF is applied to the first node of the first coupling capacitor and is amplified by the inverter/amplifier stages.

In a typical design, the inverter/amplifiers are implemented as multiple stages. The first stage amplifier has shorter gate length—mainly for high-speed operation, along with low gain, to minimize any channel-length-modulation effect. The second-stage amplifier has a longer gate for higher gain, but slower operation. Also, to avoid undesired clock feedthrough common in transfer gates, the gate widths of the p- and n-channel transistors of TG1 and TG2 are designed to have the same gate-drain and gate-source capacitances.

One of the main drawbacks of this type of circuit is its current consumption. During the autozeroing phase, when the inputs of the inverter/amplifiers are forced equal to their corresponding outputs, the currents flowing through the amplifiers are at their maximum. The common solution for such a problem is to reduce the width-to-length ratio of the amplifiers. Unfortunately, this solution affects the comparator’s gain and speed.

The Sony IMX011 is a 2.1-Mpixel CIS with three metal layers and one poly layer built using 0.18-micron CMOS technology. It is distinguished by using an improved chopper-type comparator (Fig. 3b).

The circuit structure and operation is almost like that of Figure 3a, except for the addition of the voltage-controlled current sources connected to the sources of the p-channel transistors in each stage. The current flowing through the inverter/amplifiers are then controlled through the input node V\[subscript]BCC\[/sub] at the top of the schematic.

By varying the voltage potential on V_BCC, the current flowing through the inverter/amplifiers can be reduced almost to zero in standby mode, allowed to remain at maximum during the auto-zeroing phase, or set at an optimal value during amplification or sampling. On the input side, transfer gate 369 and switchable MOS capacitors provide clock feedthrough compensation.

In the Samsung S5K3AAEA03 and S5K3BAFB CMOS image sensors , a similar approach is used (Fig. 3c). The first IC is a 1.3-Mpixel CIS with four metal layers and one poly layer that’s built on 0.18-micron CMOS technology; the second is a 2-Mpixel CIS with four copper metal layers and one poly layer that’s built on 0.13-micron CMOS technology.

In this example, both of the inverter/amplifier stages consist of two cascode p-channel transistors and two cascode n-channel transistors. Further, the first stage is connected to an n-channel voltage-controlled switch, while the second stage is connected to a p-channel voltage-controlled switch.