The rapid adoption of PCI Express (PCIe), is delivering higher bandwidth to an ever-growing number of industry segments. With PCIe Gen2 now firmly establishing a foothold, PCIe Gen 3—and its doubling of effective data rate—is already on the launching pad.
This article will focus on some of the key physical-layer features and serial/deserializer (SERDES) decisions that make PCIe the success it’s become, then address the critical “curves ahead” designers will face with Gen 3. In addition, it details the pros and cons of some of the critical physical-layer tradeoffs necessary for designers journeying into the world of PCIe Gen 3.
AT THE PHYSICAL LAYER, WHAT IS PCI EXPRESS?
PCIe physical layer has its genesis in Fibre Channel. Common in both, the eight bits of data presented for transmission are encoded into 10-bit symbols. Three functions follow from 8B/10B adoption: limiting maxim data run length; error detection; and limiting data wander.
Maximum run length: With 8B/10B encoding, effectively, the maximum number of bit intervals for which there can be no data transition is five. Data transitions are critical for clock recovery. At the time of initial adoption, the typical clock and data recovery mechanism consisted of voltage-controlled oscillator (VCO)-based PLL designs. Even with a distributed common reference—as is done in PCIe—with PLL-based recovery, long absences of data transitions results in the inability of the VCO to correct for and maintain absolute data lock. If severe enough, this drift results in burst errors.
By ensuring a worse-case transition density, early SERDES designers had a means of ensuring clock recovery with PLL-based designs and could progress on the development of physical link that became Fibre Channel and later PCIe. As loop techniques and low leakage charge pump technology improved, the stringency on run length became less critical. And too, as discussed later, the advent of Delay Lock Loop clock/ data recovery circuits, when operated under the condition of a distributed common reference clock, make reliance on data run length even less a concern.
Error detection—running disparity: In PCIe (as well as Fibre Channel) 8 bit sequences are segmented into 10 bit symbols. Symbols are further divided into two sub-classes, Data and Control. Control symbols allow physical link action, such as channel alignment, packet start, or skips. The Comma symbol is a familiar example. The data symbols are the encoded information. These symbols (data and control) can have either a positive, negative, or zero disparity—that is, disparity defines the count difference between the number of 1s and 0s in the symbol. By coding rule, the disparity is limited to +1,-1, or zero. A +1 disparity means there are six 1s and four 0s in the symbol; the reverse for a negative disparity.
Disparity has several error-checking benefits. At the interface of the receiver, any symbol received with a disparity greater than 1 can be flagged as a potential bad symbol. In addition, the protocol requires that, if a symbol with positive disparity is sent at one instance, the next symbol must be negative or zero disparity—this is known as running disparity. This “running tab” helps in both error detection and signal integrity, as we’ll see next.
Data wander: PCIe is an ac-coupled protocol. Long sequences of unbalanced data disparity will result in data wander, which is a desensitization of the receiver due to the differential lines developing an offset.
To illustrate the effects of data wander on a differential receiver, a simple circuit is shown with two different pattern extremes, excessive to demonstrate the point (Fig. 1). The circuit is a simple, ideal buffer with a common mode of 2.5 V, ac-coupled into 50-Ω lines.
A series of plots show the difference as seen at the input to a 50-Ω terminated receiver under alternate data patterns (Figs. 2, 3, and 4). The bit rate is 2.5 Gbits/s (Gen1). As can be seen from the inflection at 33 µs in the composite figure, the pattern shifts from a purposely poor dc balanced input with long non-transition periods, to one for which the run length and 1/0 bit balance is similar to 8b/10b encoding (Fig. 2). Observing the zoom views, if the balance is poor with long periods of no bit change, the available difference signal at the receiver is reduced—here the longest static period is repeated at 32 ns (80 bits) long (Fig. 3).
The zoom view of the balanced code shows the differential signal at the receiver bears close resemblance to the signal launched at the input (Fig. 4). In a real system, if no encoding (or poor encoding) schemes were used, the signal at the receiver would result in dc modulation. The effect is a reduction in channel margin, which becomes more significant with longer channels because of their higher losses. Also, as discussed later, data wander can present special problems to some adaptive receiver structures as they attempt to optimize the incoming data pattern.
OTHER PCIe PHYSICAL-LAYER FEATURES
Receiver detection: PCIe uses an ingenious means to recognize both the presence of a physical link and channel width. The specification exploits the fact that an un-terminated, ac-coupled transmission line will have a very different charge time when the line is terminated versus open. Each PCIe transmitter, at the commencement of linkup, produces a low-frequency “ping” on each of the differential TX outputs. The transmitter includes a simple detection circuit to monitor the line response to this ping. With no receiver attached, the edge rate (and amplitude) of the line change is much higher than when a receiver is present. Because the specification has a defined range of coupling capacitance and the receiver termination, a distinct, detectable time constant range defines when a receiver is present or not.