Over 40% of the papers presented at this year's ISSCC were communications- or networking-oriented. That was to be expected given this year's theme, "The Internet Age: Technologies Driving Digital Convergence." Memory, microprocessor, and other digital themes dominated in the past. But today, RF and wireless are the hot topics along with optical communications. This year, the focus was on the fastest growing wireless areas such as cell phones, wireless LANs, and Bluetooth.
Even as RF operating frequencies get higher and data rates for optical and other serial data continue to rise, there's a tendency to use CMOS exclusively where possible. While some biCMOS and SiGe bipolar devices are still used, it's amazing what you can do with 0.18- and 0.25-µm CMOS. You can put more on a chip and have it operate at frequencies over 40 GHz. Consequently, single-chip designs at microwave frequencies will promise lower chip cost and lower power consumption in future designs.
Perhaps the greatest challenge facing radio designers is the receiver. After looking through almost two dozen papers on single-chip UHF (800-900 MHz) and microwave (1.2, 1.8/1.9, and 2.4 GHz) receivers, some common trends and design solutions are noticeable.
Receiver architectures are a mix of conventional superheterodyne designs such as direct-conversion (zero-IF) and low-IF designs. Direct conversion is highly desirable, as it removes the need for expensive off-chip SAW filters. This design is difficult to achieve, however, since it results in dc offsets, increased flicker noise, local-oscillator (LO) feedthrough to the antenna, and LO pulling by the power amplifier (PA).
Yet some designers have conquered these problems with innovative techniques. Some direct-conversion designs presented include a single-chip 802.11b transceiver wireless LAN chip from Philips Semiconductor, Sunnyvale, Calif. (paper 13.5), a 3G WCDMA receiver from Finland's Helsinki University of Technology (paper 18.1), and a 930-MHz 4FSK receiver from the Hong Kong University of Science and Technology (paper 18.4).
Most designs use the traditional single-conversion superheterodyne approach. Popular single-IF frequencies are 190 and 200 MHz, or 120 kHz for low-IF designs. Low-IF designs avoid direct-conversion problems and eliminate the external SAW filter since on-chip filters can be implemented.
Starting with the input, most designers have settled on the cascode configuration for their low-noise amplifiers (LNA). This architecture uses two transistors in series to avoid the effects of positive feedback from output to input (Miller capacitance), which produce instability. No additional components are needed for neutralization. Inductors are used in the source (or emitter) for decoupling.
Paper 26.2, which comes from the Catholic University, Leuven, Belgium, shows a CMOS LNA using a cascode configuration for a super-low-noise GPS front-end at 1.2276 GHz. A noise figure of 0.79 dB was achieved.
Developed by the University of Minnesota, Minneapolis, paper 10.5 discusses an LNA for CDMA that offers a distinctive way to improve linearity. CDMA amplifiers must be unusually linear to minimize harmonics and intermodulation distortion. The procedure used significantly reduces harmonics (usually the third) with a cancellation process that increases linearity by 40 dB.
As for mixers, the Gilbert-cell design predominates in both bipolar and MOSFET form. A good number of the papers focus on image-reject mixer circuits. Originally developed to achieve single-sideband modulation without filters, this technique uses two sets of mixers. One receives the input signal and LO directly, while the other receives these signals shifted by 90°. By adding the mixer outputs, one sideband is cancelled. In a mixer, this means any image is rejected. This method allows a wider range of IF choices and simplifies frequency-synthesizer design. To be effective, however, the mixer circuits require precise phase and gain matching for the desired level of image rejection.
A unique clock and synthesizer for 2.4-GHz radios was used in two designs (Fig. 1). The synthesizer voltage-controlled oscillator (VCO) runs at 1.6 GHz. Its output is divided by two and the resulting 800-MHz signals are fed to I and Q mixers. At this stage, they're mixed with the 1.6-GHz signals and upconverted to 2.4 GHz for the transmitter. The 2.4-GHz receiver input is first mixed with the 1.6-GHz signal to get 800 MHz. Afterward, it's mixed with 800 MHz down to a zero IF.