Paper 5.3 tells of a 10-Gbit/s CDR circuit developed by the EE department at UCLA. This circuit regenerates the 10-Gbit/s (9.95328 Gbits/s actual) clock. With a pseudorandom data sequence, the jitter is 9.9 ps p-p and 0.8 ps rms.
In paper 5.6, Lucent Technologies' Optical Networking Group in Nuremberg, Germany, introduces a fully integrated 40-Gbit/s CDR and demultiplexer circuit. This IC is made with SiGe heterojunction bipolar transistors (HBTs) with an fT of 72 GHz.
Optical-processing chips covered at the conference ran the gamut from optical input amplifiers to fast serial processing circuits and laser-diode driver circuits. Paper 14.4, from the Department of Electrical and Computer Engineering at the University of Toronto, focuses on a 75-Mbit/s optical receiver that uses a common-gate transimpedance amplifier and operates from a 1-V supply.
Three papers concentrate on Sonet transceiver chips. Broadcom's paper (5.2) presents a fully integrated CMOS OC-48 transceiver. The others, 5.5 from Hitachi, Tokyo, Japan, and 5.4 from Lucent Technologies, illustrate a SiGe biCMOS OC-192 transceiver. A CDR circuit along with a 1:4 demultiplexer and a 4:1 multiplexer are included in the first circuit. The transmitter takes four serial inputs at 622 Mbits/s in 4-bit chunks and sends them to the FIFO. This compensates for any phase variations between the on-chip clock and the input clock derived from the LVDS input data.
A clock multiplier unit (CMU) obtains the external reference clock and multiplies it by 16 or 23 to get the 2.5-GHz (2.488 GHz actual) transmit clock. If forward error correction (FEC) is used, the clock frequency also can be set to 2.666 GHz. The multiplexer generates the single 2.488- or 2.666-GHz output data stream.
In the receiver, a CDR regenerates the clock from the input data stream. A demultiplexer takes the single input bit stream and regenerates the four 622-Mbit/s signals at the outputs.
Hitachi's 10-Gbit/s transceiver suits OC-192 Sonet applications, or possibly 10-Gbit Ethernet products. This transceiver multiplexes 16 622-Mbit/s data paths into a single 10-Gbit/s (9.968 Gbits/s actual) OC-192 signal. As in the previous design, a FIFO compensates for phase differences.
In the receiver, the 10-Gbit/s serial input is passed through the CDR and then to a 1:16 demultiplexer to recover the 16 622-Mbit/s signals (Fig. 2). The receiver also has an error detector and a pseudorandom bit stream (PRBS) generator for test purposes. The high speed is obtained by using HBTs made with SiGe on the inputs and outputs and MOSFETs on the internal circuitry.
Some other papers include two on Gigabit Ethernet transceivers by Marvel Semiconductor, Sunnyvale, Calif.; two on DSL analog front ends by Texas Instruments, Dallas, Texas, and Infineon Technologies, Munich, Germany; a universal set-top box on a chip by Broadcom; and a direct-access-arrangement (DAA) chip for use in the PSTN by Silicon Labs, Austin, Texas.