Minimum shift keying (MSK) is a popular modulation method for computer data transmission. When compared to commonly used FSK modulation, MSK offers a narrower frequency bandwidth and improved phase performance. Since MSK modulation is a continuous-phasemodulation technique, its transmitted data must be synchronized with an internal MSK clock.
Typical computer data communications involve the use of an RS-232 port. RS-232 communication, however, operates using asynchronous data transmission. This makes it difficult to interface RS-232 ports to MSK modems. A special synchronization circuit is required to provide the interface between an MSK modem and an RS-232 port (see the figure).
In this circuit, the D flip-flop IC1 detects the negative-going edge of the RS-232 start bit. When the start bit is detected, counters IC2.1 and IC2.2 are enabled to read the RS-232 incoming data. At the same time, these counters clock eight bits of the RS-232 data (or seven bits + parity) into the serial-to-parallel shift register (IC3). Data loading for the RS-232 is completed on the clock’s ninth edge. Once this occurs, the eight received data bits are transferred to the parallel-to-serial shift register (IC5) and counters IC2.1 and IC2.2 are enabled.
The MSK modem’s synchronousclock input (IC5) is then used to reclock the data back out of the shift register, restoring its serial format. This concludes the serial/parallel-parallel/serial circuit operation. Any variations between the RS-232 port’s transmit timing and the MSK modem’s synchronousclock timing are absorbed.
Implemented using a Altera Max7000-series CPLD, this circuit performs well.