Take Advantage Of All That USB On-The-Go Has To Offer

AUTO CONNECT
In the OTG HNP-state diagram, when the A-device is in A_SUSPEND state, it must enable its pull-up resistor on the D+ line within 3 ms upon detection of the B-device being disconnected. If the auto-connect feature is implemented in the hardware, and the feature is enabled when the A-device enters the A_SUSPEND state, then the A-device will automatically enable its pull-up on the D+ line upon detecting a disconnection.

AUTO RESET
In the OTG HNP-state diagram, when the B-device is in the B_WAIT_ACON state, it must send bus reset within 1 ms upon detection of the A-device being connected. If the auto-reset feature is implemented in the hardware, and the feature is enabled when the B-device enters the B_WAIT_ACON state, the B-device will automatically send bus reset upon detecting a connection.

BUS RESUME
In the USB 2.0 spec (section 7.1.7.7), the downstream or upstream device may interpret any non-idle signal as a resume signal from the upstream or downstream device. In the OTG spec, if the dual-role B-device is in B_WAIT_ACON state, or the A-device is in A_SUSPEND state (and the B-device is enabled for HNP), then only a J-to-K transition on the bus will be treated as a bus resume. Note that a J->SE0->K could also be treated as a bus resume, if the SE0 time is less than 2.5 µs.

POWER DOWN AND WAKE-UP
For a battery-powered OTG device, the OTG controller will be put in the power-down mode if the device is not in a session. This significantly reduces power consumption. (Typically, the current draw should be less than 50 µA.) In this mode, both the DC and the HC are suspended. The PLL, oscillator, and charge pump are turned off.

To support an OTG device when it must respond to an OTG event, a slow or Lazy is kept running while the chip is in power-down mode. The Lazy clock runs a very low clock frequency during suspend mode that, together with a very low "suspend" power consumption, allows for easy design of peripherals that comply with ACPI, OnNow, and USB power-management requirements. An OTG event will be detected and wake up the chip (that is, enable the PLL and oscillator). The interrupt can be generated after the clock is up, if the corresponding interrupt is enabled. The OTG controller should also support software wake-up. If no OTG event is detected, but the application running on the OTG device wants to use the USB bus, software can wake up the OTG controller and start a session.

HUB SUPPORT
Dual-role devices can handle hubs. However, standard USB hubs don’t support the signaling methods used for the SRP and HNP. Therefore, when an A-device is directly connected to a standard hub, the A-device is prohibited from issuing a command that would enable the downstream device to expect or initiate HNP. So, when a peripheral is connected downstream of a hub, it can’t become a Host anymore.

OTG TRANSCEIVER
An OTG transceiver is a physical-layer device that interfaces between an OTG controller core and the USB bus. Beyond the standard USB transceiver function, an OTG transceiver provides analog parts for use by SRP/HNP. These include the 5-V charge pump, voltage-level comparators, pull-up/pull-down resistors, and the ID detector. Two classes of OTG transceiver prevail in the market. One is a full-speed OTG transceiver that supports USB low and full speeds. The other transceiver adds Hi-Speed USB support. Two transceiver types exist in the market because Hi-Speed USB consumes more power and requires a larger chip package. Both transceivers have standard interfaces defined by industry consortiums of key USB providers. For applications that don’t require the 480-Mbit/s high-speed data rate, the full-speed OTG transceiver is a more economical choice.

The de facto industry-standard USB OTG transceiver is the ISP1301, the industry’s first USB OTG transceiver that has been designed into the reference platforms of major handset and baseband communications manufacturers. It supports the mini-USB analog car kit standard, as well as a transparent I²C/UART mode on the D+/D- (Fig. 2).

Given the ubiquity of USB in the world today, USB OTG will enjoy the same widespread acceptance and use. In this article, we discussed the requirements for an OTG system that easily integrates onto an ASIC based on different processors and operating systems. The OTG tutorial page can be found at: http://www.semiconductors.philips.com/buses/usb/products/otg/tutorial

Alan Chang is a chief design engineer with Philips Semiconductors. He holds an MS in electrical/electronic engineering from Iowa State University, Ames, Iowa. Chang can be reached at alan.chang@philips.com.

Zhong Wei Wang is a chief applications engineer with Philips Semiconductors. He holds an MSEE from the Shanghai Institute of Metallurgy at the Chinese Academy of Sciences, China. Wang can be reached at wang.zhong.wei@philips.com.

Shaun Reemeyer is a senior IC design engineer with Philips Semiconductors. He holds a bachelor of engineering with honors from the University of Tasmania, Australia. Reemeyer can be reached at shaun.reemeyer@philips.com.

AUTO CONNECT
In the OTG HNP-state diagram, when the A-device is in A_SUSPEND state, it must enable its pull-up resistor on the D+ line within 3 ms upon detection of the B-device being disconnected. If the auto-connect feature is implemented in the hardware, and the feature is enabled when the A-device enters the A_SUSPEND state, then the A-device will automatically enable its pull-up on the D+ line upon detecting a disconnection.

AUTO RESET
In the OTG HNP-state diagram, when the B-device is in the B_WAIT_ACON state, it must send bus reset within 1 ms upon detection of the A-device being connected. If the auto-reset feature is implemented in the hardware, and the feature is enabled when the B-device enters the B_WAIT_ACON state, the B-device will automatically send bus reset upon detecting a connection.

BUS RESUME
In the USB 2.0 spec (section 7.1.7.7), the downstream or upstream device may interpret any non-idle signal as a resume signal from the upstream or downstream device. In the OTG spec, if the dual-role B-device is in B_WAIT_ACON state, or the A-device is in A_SUSPEND state (and the B-device is enabled for HNP), then only a J-to-K transition on the bus will be treated as a bus resume. Note that a J->SE0->K could also be treated as a bus resume, if the SE0 time is less than 2.5 µs.

POWER DOWN AND WAKE-UP
For a battery-powered OTG device, the OTG controller will be put in the power-down mode if the device is not in a session. This significantly reduces power consumption. (Typically, the current draw should be less than 50 µA.) In this mode, both the DC and the HC are suspended. The PLL, oscillator, and charge pump are turned off.

To support an OTG device when it must respond to an OTG event, a slow or Lazy is kept running while the chip is in power-down mode. The Lazy clock runs a very low clock frequency during suspend mode that, together with a very low "suspend" power consumption, allows for easy design of peripherals that comply with ACPI, OnNow, and USB power-management requirements. An OTG event will be detected and wake up the chip (that is, enable the PLL and oscillator). The interrupt can be generated after the clock is up, if the corresponding interrupt is enabled. The OTG controller should also support software wake-up. If no OTG event is detected, but the application running on the OTG device wants to use the USB bus, software can wake up the OTG controller and start a session.

HUB SUPPORT
Dual-role devices can handle hubs. However, standard USB hubs don’t support the signaling methods used for the SRP and HNP. Therefore, when an A-device is directly connected to a standard hub, the A-device is prohibited from issuing a command that would enable the downstream device to expect or initiate HNP. So, when a peripheral is connected downstream of a hub, it can’t become a Host anymore.

OTG TRANSCEIVER
An OTG transceiver is a physical-layer device that interfaces between an OTG controller core and the USB bus. Beyond the standard USB transceiver function, an OTG transceiver provides analog parts for use by SRP/HNP. These include the 5-V charge pump, voltage-level comparators, pull-up/pull-down resistors, and the ID detector. Two classes of OTG transceiver prevail in the market. One is a full-speed OTG transceiver that supports USB low and full speeds. The other transceiver adds Hi-Speed USB support. Two transceiver types exist in the market because Hi-Speed USB consumes more power and requires a larger chip package. Both transceivers have standard interfaces defined by industry consortiums of key USB providers. For applications that don’t require the 480-Mbit/s high-speed data rate, the full-speed OTG transceiver is a more economical choice.

The de facto industry-standard USB OTG transceiver is the ISP1301, the industry’s first USB OTG transceiver that has been designed into the reference platforms of major handset and baseband communications manufacturers. It supports the mini-USB analog car kit standard, as well as a transparent I²C/UART mode on the D+/D- (Fig. 2).

Given the ubiquity of USB in the world today, USB OTG will enjoy the same widespread acceptance and use. In this article, we discussed the requirements for an OTG system that easily integrates onto an ASIC based on different processors and operating systems. The OTG tutorial page can be found at: http://www.semiconductors.philips.com/buses/usb/products/otg/tutorial

Alan Chang is a chief design engineer with Philips Semiconductors. He holds an MS in electrical/electronic engineering from Iowa State University, Ames, Iowa. Chang can be reached at alan.chang@philips.com.

Zhong Wei Wang is a chief applications engineer with Philips Semiconductors. He holds an MSEE from the Shanghai Institute of Metallurgy at the Chinese Academy of Sciences, China. Wang can be reached at wang.zhong.wei@philips.com.

Shaun Reemeyer is a senior IC design engineer with Philips Semiconductors. He holds a bachelor of engineering with honors from the University of Tasmania, Australia. Reemeyer can be reached at shaun.reemeyer@philips.com.