Test 4: Power-Supply Sensitivity. Through this test, the designer can see what may happen to the physical-layer device when it's placed in a more complicated/noisy environment than the MII MAU. When included with power-supply and temperature variation, it also may be used in combination with the previously mentioned tests (Fig. 4).
Most physical-layer-device MII MAUs have power split into separate VCC planes. A signal generator coupled with a slew-rate-controlled buffer can inject noise into a system. All frequencies should be injected into each and every isolated plane. Some physical-layer devices need a clean or regulated power supply to function properly. Test cable length and BER with a noisy system. It's likely that cable length will decrease as noise to the system increases.
Test 5: Receive Equalization/Jitter. This one's more complicated than the previous tests, but very useful in exercising the physical-layer device in worst-case scenarios. The key to most of these devices is their ability to properly receive and decode a signal, however distorted it may become, from the network. This test is becoming more widespread as users start to understand the importance of exercising the receive equalizer, as well as the fact that for interoperability, it must be able to meet the worst-case TP-PMD specification (Fig. 5).
Starting with basic ideal binary data, it's then modified to reflect a certain set of parameters. For a worst-case scenario, those parameters would include ppm drift, rise/fall time, jitter, cable loss/phase delay, transformer effects, crosstalk, etc. The end result is a waveform representing a packet that has been modified with the above parameters.
For converting the data, it's typical to use a tool like Mathcad. The modified data is sampled and converted to a series of analog voltages—hence an analog waveform. This waveform is supplied to the analog waveform generator, and sent to the DUT via BNC cables connected to the Receive differential signals. The ability of the DUT to properly receive the packet is then analyzed using the network analyzer, in this case a SmartBits type of tester. An external power supply tests the DUT's performance over different voltage ranges.
When evaluating a 10/100 physical layer, the first set of tests done on the part should include a subset of TP-PMD testing. This will allow you to test, in part, the transmitter of the device. First, get a look at the transmit waveforms of the device while it's transmitting 100-Mbit idles. Optimally, all measurements should be done at the RJ-45. With a BNC-to-RJ45 cable, this is easily done. If using simple oscilloscope probes, the next best option is hooking to the transmit out pins on the cable side.
Take care to have a 50-Ω impedance to each probe. The differential voltage amplitude should be 2 V, within 5% per IEEE specifications. A low jitter profile from the PHY transmitter will help a marginal far-end PHY receive your signal. Focusing on an edge of the differential signal, look at the eye opening several microseconds after the trigger point. Measure the jitter and divide by two to determine the part's jitter. TP-PMD requires a jitter of less than 1.4 ns.
Other system-level tests can be run by routing the signal through intermediate devices, such as repeaters and switches. Multiple nodes can connect through a hub. A generic view of the system performance can be gathered by monitoring each node's ability to transmit and receive with that hub. Then, interoperability can be tested by attaching nodes from various vendors to the hub and alternating cable distances, etc. This type of system-level testing can be quite extensive and time-consuming. Unfortunately, it's usually not done thoroughly until user problems arise.
While 10-Mbit and 100-Mbit physical-layer and transceiver testing can be exhaustive, IEEE standards and independent test labs like that of the University of New Hampshire can provide much-needed help. The results are stable, interoperable networks that operate with the same degree of reliability as existing 10-Mbit/s environments. And they provide for future operation at 100 Mbits/s.
By applying the above tests, the designer can quickly evaluate the performance of a physical-layer device, as well as understand how much work will be required to implement that solution in a system-level design. Having passed the above tests, the Enable Semiconductor 5VSingle, 3VSingle, and 3VCardbus devices (now available from Lucent Technologies' Microelectronics group) each reflect successful IEEE and UNH testing. They may be used as a benchmark for testing similar physical-layer devices.
The tests outlined in this article serve as a beginning to understanding and testing physical-layer devices. Once that basis is understood, the designer can appropriately grasp, in conjunction with other IEEE and interoperability testing, the limits of the physical-layer device and design networking systems.
Resources:
- IEEE—802.3u 100BASE-T Fast Ethernet Standard: http://standards.ieee.org/catalog/IEEE802.3.html.
- University of New Hampshire: UNH provides system-level testing for Fast Ethernet Consortium members. Its test suite is growing and includes a very adequate section on auto-negotiation at this time. It also has a variety of vendors' products that it can use to do interoperability testing.