Design Issues |
Actel |
Altera |
Lattice |
Xilinx |
Top Issues Application
Engineers Deal With Daily |
JTAG testing or programming through TAP
interface; integration and modification of IP
cores; SSO mitigation |
Power consumption and performance
optimization; debugging; interface complexity;
signal Integrity; system complexity |
Meeting hardware and design timing closure;
SERDES implementations; pc-board and FPGA
noise management; multiple clock domains;
power management and sequencing;
configuration requirements |
Configuration accounts for about16% of
inquiries, and embedded design issues account
for about13% of inquiries; the top issues relating
to the ISE design tools include mapping, place-and-route, Project Navigator, and the XST synthesis tool; additional challenges include
dealing with memory interfaces, IP integration,
and power management |
I/O signal assignment
ordering |
Lay out dedicated I/O banks and keep SSO in
mind while doing so; switching busses should be
spread out across the die and away from PLL
supply pins and asynchronous I/Os; then, assign
I/Os within each bank; differential pairs should be
assigned first followed by I/Os that require VREF |
No special pin assignment sequencing
necessary, but do pay attention to each pin's
capabilities as some are specialized for specific
purposes, such as PCI Express |
Proper I/O floor planning is required; start with
specialized I/Os, such as DDR2, then assign
general I/Os, such as LVTT;.pPay special
attention to multi-function pins, such as VREF,
high-speed clock inputs, and PLL/DLL inputs |
Typically, FPGA pins that have the tightest
constraints should be locked down first; a typical
order for pin assignment might be: 1. input
global/regional clocks and FPGA configuration
pins; 2. MGT (SERDES), high-speed single
ended interfaces, differential signals, and voltage
reference pins as dictated by the I/O standard for
a given region; 3. buses that require grouping
into adjacent package pins on the FPGA for
internal timing or pc-board layout; 4. slow signals
like reset; there are several tools and online
resources to assist with this process. |
Intrabank incompatible
I/O standards, different
voltage references, and
other bank/region
compatibility issues |
Make use of Designer software environment,
which simplifies the process and provides
guidance where necessary |
The goal is to make dealing with incompatiblities
as easy as possible; to this end, Altera enables
pins to support multiple I/O standards across
multiple voltage; for example, a pin powered by a 2.5-V supply can accept 3.3-V inputs on most
devices; also, most pins are designed to enable
hot-socketing, where the FPGA can act as the
interface on the board that is being plugged into
a live system |
Plan ahead to avoid potential downstream pcboard issues and make use of ispLEVER I/O Assistant early in the design |
Derive two spreadsheets; first list all design I/Os
and their electrical properties and preferred
location on the package; then create
classes/groups of signals sharing compatible IO
power/reference voltage; second, list all the device I/O and their properties; sort that table by
I/O bank; then filter out all dedicated or
previously assigned I/Os from both spreadsheets; match I/Os with the appropriate
I/O banks; there are several online resources
available |
Dealing with FPGA to
pc-board issues such
as SSO, decoupling,
routability, escape area,
and escape planning
with respect to signal
layers and thermal
issues |
Proper decoupling, termination, and layout on
the pc board are important; however, it's best to
prevent SSO altogether at the source by
spreading fast-switching outputs across the die;
the pins of QFPs have greater inductance than
BGA packages; place sensitive I/Os near VCC or GND pads; create mini groups within a bus and
stagger their outputs by more than 1 ns |
Check online for literature and seminars that
address these topics; published escape routes
are available |
Distribute the capacitive loads and pin
assignment, optimize the drive current, control
output slew rates, and reduce the output voltage
swing where possible; decoupling examples
based on eval boards and documentation are
available; for BGA packages, use two signal
layers for every two rows of balls; use software to
analyze thermal issues. |
Refer to the following whitepaper on Xilinx.com:
"Methodologies for Efficient FPGA Integration
into PCBs " |
Handling of differential
signals |
Use a standard termination scheme |
Make use of on-chip termination for LVDS and
differentials and keep signals closely coupled; online documentation is available |
Detailed ac and dc coupled termination schemes
are provided for different differential standards;
apply differential pc-board layout rules to keep
equal trace lengths between positive and
negative traces and between data channels of
the transmit and receive side of the differential
interface; see online documentation for more
details |
Refer to the following whitepaper on Xilinx.com:
"Transmitting DDR Data Between LVDS and RocketIO CML Devices " |
Handling of various
clocking schemes |
Use the Libero IDE 7.3 tool's block-based
design methodology for clock distribution to
instantiate a global clock placeholder (CLKINT);
then the global buffer can be built into the top
level of the design |
Their tools provide automated methods of
choosing which clocks to use; online
documentation is available |
Use global clocks with low skew to reach any
device register; when shorter injection times or
smaller skews are required, use local clocks; for
the best possible injection, setup, and hold
times, use edge (I/O) clocks |
Virtex-5 devices contain clock management to
address complex timing requirements; refer to
Xilinx's online resources for more on these issues |
Combining IP blocks
and IP shopping |
Using IP blocks can create natural boundaries
that limit what automation tools can optimize, yet
may be useful for debugging and can aid with an
incremental design flow by limiting changes; for
third-party IP, ensure it was designed for the
FPGA architecture you are targeting and whether
it is efficient in size and performance; good IP
also comes with thorough testbenches and high-quality documentation; you may also want to
check IP core heritage along with the supplier
before you commit usage |
Use SOPC Builder , Altera's automated system
development tool, to tie IP blocks together and
build a component; there is more information
online |
To minimize timing closure issues, check that
proper timing analysis, timing simulation, and
hardware validation were performed on
purchased blocks, or you will need to do this
yourself; ensure that each block has adequate
timing margin for the target FPGA; use the IPexpress tool to "test drive" IP in hardware; IP
cores should be built on some form of a common Control Plane Interface (CPI) |
The main challenge in combining IP blocks is
ensuring timing and resource requirements are
met; when shopping for IP, confirm how the IP
vendor has verified and validated the IP with
respect to quality and ease of use; minor
challenges in combining IP blocks are primarily
caused by subtle differences in what is delivered
by the IP vendor and the format of those
deliverables |
Handling of timing
issues causing the
biggest problems |
Min delay and hold-time analysis are often
overlooked; external hold-time and cross-clock
domain paths tend to cause most timing-related
issues resulting in hardware failures; perform
both back-annotated timing simulation, static
timing analysis, and simulation for functional
verification, and note that static analysis provides
the best timing coverage; the SmartTime timing
analyzer allows for entering of external input and
output delays and then performs the calculations |
For on-chip timing, use caution with the FMax
parameter; the TimeQuest timing analyzer and
physical synthesis helps; For off-chip timing,
source synchronous used for many interfaces
with LVDS can be problematic; TimeQuest can
also be used for source-synchronous interfaces |
Timing windows are getting smaller with higher
frequencies; clock domain transfer at high
speeds, race conditions, and hold time violation
are the most problematic; a combination of
careful timing analysis along with using the ispLEVER tool can help identify the areas and
help resolve the issues; due to the extremely high performance of the
Lattice FPGA fabric, the probability of hold time
violations has significantly increased |
No answer provided |
Modifications to tool
suite to help overcome
the above issues |
Today, designers can implement fairly complex
system-on-a-chip on modern FPGAs, and they
require features from traditional logic design
tools, as well as those from analog, DSP, and
processor design tools; to support cross-functional engineering disciplines, their tools
integrate the look and feel of tools from each
discipline |
The quality of the tools is a key focus area with
the goal of providing easy-to-use tools that
deliver a high quality of results; this includes
emphasizing the eliminating of internal errors and
crashes and reducing compile time and PC
memory usage; PowerPlay power analysis and
optimization technology enables designers to
accurately analyze and optimize both dynamic
and static power consumption |
Power, SSO, and FPGA constraint planning, runtime/turnaround time improvements, ispTRACY debugging tool, pre-built IP, RTL Analysis and
improvements, and documentation (HDL
Explorer) |
No answer provided |