A recent arrival on the 3D IC wafer-level chip-scale package (WLCSP) front, Deca Technologies, promises to slash heretofore unsolvable packaging costs for 3D ICs drastically with a series of WLCSP products that offer speed, low cost, and flexibility options not available with present 3D ICs using TSVs. Deca expects to be able to go from the design to the manufacturing step in less than an hour and says it will have products on the market sometime this year or next.
IMEC researchers have developed a WLP technology for packaging microelectromechanical-systems (MEMS) devices. WLP is essential for MEMS devices to protect the fragile MEMS structure from the hazards of the back end of the assembly process as well as the device’s operating environment. Technically, MEMS devices are 3D ICs due to the mechanical nature of their operation, which requires space for the sensing element to work.
This comes after an announcement by SUSS MicroTec that it is partnering with SVTC Technologies by supplying the latter with alignment and bonding equipment for MEMS 3D IC package development. They will focus on new WLP processes and solutions.
IMEC has demonstrated the fabrication of extremely small sealed cavities (less than 1 pL in volume), directly on 200-mm silicon wafers using thin-film nanoporous alumina membranes (Fig. 3). The thin-film technology bolsters the device’s strength and the package’s air-tight hermeticity.
To remove the sacrificial layer and to form the microcavity between the MEMS element and the capping layer, lithographically defined release holes are made. A cylindrical 2- to 3-µm thin free-standing cap layer (15 to 20 µm in diameter) is used whose nanopores serve as release etch holes to keep the package’s sealing materials from leaking into the cavity underneath.
One of the leaders producing environmentally resistant MEMS packaging, ePack, employs a robust packaging process in an oven-controlled vacuum and hermetically sealed environment of 200°C to 400°C. The MEMS device is equipped with a cap and a platform for thermal and vibration isolation. Heaters and temperature sensors are used on the platform (Fig. 4).
Vacuum packaging and process cleanliness are extremely important for MEMS devices used in military, industrial, and medical environments.
“Achieving high levels of vacuum is a very challenging task,” explains Jay Mitchell, CEO and cofounder of ePack along with Sangwoo Lee. He cites vacuum levels needed to make their MEMS device on the order of 7.6 mTorr, which is equivalent to one one-millionth of an atmosphere, and more than 100 monolayers of water vapor in a cleanroom. “It is very important to design your packaging solution along with your sensor. This should not be an afterthought,” he says.
Mary Ann Maher, founder of SoftMEMS LLC, stresses the importance of using software co-design principles for MEMS-based products. She points out that software can be used to validate new package concepts where the TSVs in MEMS devices are simulated to determine the characteristics of the via and to find fabrication errors. The simulator emulates the buildup of materials used to construct the via.
Thermo-mechanical simulations are performed as each layer is deposited to determine stress and temperature behavior (Fig. 5). Electromagnetic simulations are used to determine the via’s electrical behavior.
FPGAs at 2.5D?
FPGAs are making progress in using silicon TSVs for 3D ICs, particularly in a relaxed-geometry mixed-signal die, where TSVs are on a 50-µm pitch or greater and there are no concerns for modeling mutual-inductance or even capacitive coupling effects. Many in the semiconductor industry refer to so-called 3D FPGA ICs as 2.5D ICs.
Xilinx’s Virtex-7 2000T FPGA packs 6.8 billion transistors using four chip slices and links them together using a silicon interposer layer, all without the need for I/O buffers (Fig. 6).
There are no logic or interface elements in the TSVs. TSMC is making the silicon interposers, which allow the redistribution of the FPGA interconnections using TSVs that mate to copper balls on a substrate package that uses a controlled-collapse chip connection (C4).
Not everyone is convinced the path to 3D silicon ICs rests on developing TSVs. Zvi Or-Bach, president and CEO of startup MonolithicIC 3D Inc., argues that high-density monolithic 3D ICs are possible without the need for TSVs. His patented IP Ion-Cut method uses crystalline silicon that can be formed above copper wiring, which can be useful for making 3D logic, memory, FPGAs, and electro-optic functions, at 1000 times higher densities than TSVs (Fig. 7).
Other materials besides silicon interposers, like glass and carbon nanotube interposers, are also being investigated in the search for the ideal 3D TSV solution. Tests on glass interposers are underway at Taiwan Semiconductor Manufacturing Corp. (TSMC) and the Georgia Institute of Technology.