Thanks To TSVs, 3D IC Packaging Gets Set To Tackle Tough Challenges

1 of Enlarge image

Fig 1. The system-in-package approach is part of the trend toward thinner and more integrated 3D IC packages for CPUs, GPUs, and FPGAs for use in camera modules and wireless products, where high performance and form factor are the driving forces. The use of through-silicon vias (TSVs) will lead to package thicknesses of about 0.7 mm. (courtesy of Renesas Corp. as well as “3D TSV: Moving Past PowerPoint Engineering: Issues And Market Adoption,”

Fig 2. Package-on-package (PoP) (a) and system-in-package (SiP) (b) implementations are possible using embedded wafer-level BGA (eWLB) double-sided packaging. (courtesy of “Development of Next Generation eWLB Packaging,” International Wafer Level Packaging Conference)

Fig 3. 3D silicon interposers can be used for stacking memory, FPGA, sensor, and ASIC devices, according to RTI International. (courtesy of “Recent Progress in 3-D Integration Technology Development at RTI,” TechSearch International, 3D ASIP Conference)

Fig 4. By moving the high-voltage transistors needed for anti-fuse programming underneath the 3D structure, FPGAs with densities comparable to ASICs can be stacked in a 3D format without the need for TSVs, according to NuPGA Corp. (courtesy of NuPGA Corp.)

Fig 5. Ziptronix calls its direct bond interconnect (DBI) process the lowest-cost 3D TSV process that does not suffer from lower yields as line geometries shrink. (courtesy of Ziptronix)

As designers strive to achieve true 3D IC packaging with through-silicon vias (TSVs), they have had some mixed results. First, there’s the good news. The implementation of TSVs is gaining momentum and garnering greater favor in the semiconductor industry.

There is the realization that semiconductor processing must gravitate toward smaller and smaller geometries in 3D formats from the present 2D formats, down from 45, 22, and 18 nm to even tinier dimensions to meet future market needs. And to that end, there have been shining examples of the advances possible in 3D packaging using TSVs for higher levels of integration.

Improvements in 3D stacking continue mostly for memory and logic functions as well as for certain types of chips like image sensors, III-V devices, microelectromechanical systems (MEMS) devices, and to some degree power devices. Witness the recent 8-Gbyte registered dual-inline memory module (RDIMM) from Samsung Electronics. It employs TSV die stacking that saves 40% of the power consumption of conventional RDIMMs, Samsung says. Many companies are ramping up their efforts to manufacture wide-I/O DRAMs that use silicon TSVs. 

Now for the sobering news. The technology is not quite there yet and lacks maturity, despite its notable achievements. One major issue lies in determining who produces the TSV. Is it the fab facility, the etching or bonding facility, the packaging house, or someone else?

The industry is grappling with these choices, proposing three different processing options: putting the via at the front end of the line (FEOL), putting it in the middle of the process, or putting it at the back end of the line (BEOL). Most 3D TSV processes use the via in the middle approach and are close to being fully ready, but they still require more improvements in production throughputs to reduce costs further.

Current wire-bonding approaches for chip stacking have made notable advances. But most semiconductor IC experts agree that when you need high performance and wide bandwidths from devices like the latest microprocessor that entail hundreds of leads within an even smaller and more confined chip area, wire bonding won’t cut it. It becomes imperative to go to the 3D TSV route.

“The greatest challenge is the lack of standards, specifications, and a clear business model for implementing this technology across the entire supply chain,” notes Larry Smith, a member of the technical staff at Sematech, an international consortium of semiconductor manufacturers. “There are also technical challenges. Based on an industry survey we conducted last September, these include reliability, a lack of consensus on how to perform temporary bonding and de-bonding to drive down costs, designing for stress management to ensure that device characteristics are not shifted by proximity to TSVs, and chip-package interactions and stresses that adversely affect reliability.”