Simultaneous-Sampling ADCs
The current drawn by a motor can be split into two components--one
produces torque, and the other produces magnetic flux. For optimal
performance of the motor, these two components should be controlled
independently.
In conventional methods of controlling a three-phase motor, the
current (or voltage) supplied to the motor, and the frequency
of the drive, are the basic control variables. However, both the
torque and flux are functions of current (or voltage) and frequency.
This coupling effect can reduce the performance of the motor.
For example, if the torque is increased by increasing the frequency,
the flux tends to decrease.
Vector control of an ac motor involves controlling phase in addition
to drive and current frequency. Controlling the phase of the motor
requires feedback information on the position of the rotor relative
to the rotating magnetic field in the motor. Using this information,
a vector controller mathematically transforms the three-phase
drive currents into separate torque and flux components.
A typical dual-channel, simultaneous-sampling ADC (AD7862) for
vector-controller applications is shown in circuit (Fig. 2). Along with simultaneous-sampling capability, the high-speed,
low-power, 12-bit ADC has two 4-µs successive-approximation ADCs
and two track/hold amplifiers.
There are four analog inputs that are grouped into two channels
(A and B). Each channel has two inputs (VA1 and VA2, and VB1 and
VB2) that can be sampled simultaneously, thus preserving the relative
phase information of the signals on both analog inputs. The critical
track/hold specifications for preserving the relative phase information
are the -3-dB small-signal bandwidth (in this case, 3 MHz), aperture
delay (20 ns), aperture jitter (100 ps), and the aperture delay
matching (200 ps). Designed for motor-control applications, the
ADC under discussion also accepts bipolar analog input ranges
of ±10 V, ±2.5 V, and 0 to 2.5 V, while operating from a single
5-V supply.
The position of the field is derived by determining the current
in each phase of the motor. Only two phase currents need to be
measured as the third can be calculated if two phases are known.
Simultaneous sampling inputs VA1 and VA2 of the ADC are used to
digitize this information.
Simultaneous sampling is critical if the relative phase information
between the two channels is to be maintained. A current-sensing
isolation amplifier, transformer or Hall-effect sensor is used
between the motor and the ADC. Rotor information is estimated
from voltage measurements from two motor windings. The other two
simultaneous inputs of the ADC, VB1 and VB2, are used to obtain
this information. Once again, the relative phase of the two channels
is important. A DSP microprocessor is then used to perform the
mathematical transformations and control-loop calculations on
the information fed back by the ADC.
Sigma-Delta (Δ-Σ) ADCs
The Δ-Σ converters discussed in this section are part of a one-chip motor
control solution, the ADMC300, variations of which are available
from a number of manufacturers. Δ-Σ converter technology is based on an oversampling technique. The
input signal is typically sampled with a one-bit converter (a
modulator) at high frequencies, typically 1 to 2 MHz (Fig. 3). The resulting high-frequency bit stream is digitally filtered
and decimated (down sampled) to the effective sample rate.
This converter technology is well-suited to a bulk CMOS process,
and is also very conducive to mixed-signal integration. The Δ-Σ converter does, however, introduce additional system-level design
constraints that will be discussed later on in this article.
Typically, the sampling of a current waveform is synchronized
with the pulse-wave-modulated (PWM) waveform to reduce the effect
of PWM ripple on the sampled data. In doing so, each of the sideband
harmonics are symmetric about the PWM switching-frequency harmonic.
By sampling at the PWM switching frequency, all the sideband harmonics
sum to dc. By sampling at the zero mean point of the current ripple,
the sideband harmonics sum to zero. This point aligns with the
synchronization pulse of a center-based PWM system (Fig. 4). The frequency spectrum of a current waveform for a single-phase
system is shown. The figure depicts the fundamental, first, second,
third, and fourth PWM ripple harmonics.
With the Δ-Σ converter, the data is modulated (sampled) at 1 to 2 MHz. Therefore,
multiple harmonics of the PWM ripple are sampled. The Δ-Σ converter architecture that is part of the ADMC300 one-chip motor
control solution was analyzed to generate the spectrum of the
current waveform as well as the spectrum of the remodulated current
waveform, respectively.
It is apparent that the PWM harmonics are indeed sampled. However,
by choosing a modulation frequency equal to the decimation factor
times the PWM frequency, the sampled PWM harmonics are aliased
to dc. As is the case in the successive-approximation approach, the
PWM harmonic content of the original current waveform are not
present in the sampled spectrum.
The synchronizing of the modulation frequency with the PWM sample
frequency is key to the effective use of a Δ-Σ in a motor application. Not doing so would require the use of
antialiasing filters to remove the harmonic content before the
current information could be sampled. Typically, this synchronizing
is not an option with discrete implementations. However, with
the integration of a Δ-Σ converter and a PWM onto the one device (ADMC300), the necessary
sampling conditions can be satisfied.
A successive-approximation ADC is typically modeled as a finite
delay that is attributed to the conversion time of the particular
device. A Δ-Σ converter, on the other hand, is a dynamic system and must be
modeled as such.
In a motor-control application, these dynamic characteristics
have to be accounted for in the design of the control system.
Failing to account for the dynamics of the Δ-Σ converter in the feedback path of a closed-loop system will impact
the robustness of the resulting controller. Both the modulator
and decimator blocks exhibit a dynamic behavior. The dynamics
of the decimator portion, however, dominates the dynamic response
of the converter. The decimation filter is described as Figure 5.
where D denotes the decimation factor and G(z) is the transfer
function of the filter. The value "z" corresponds to a sampling
delay (i.e. for a set data samples x(0) ...x(n) ...where x(x)
is the most recent sample, then z x x(n) = x(n-1).
In the case of the ADMC300, the decimation factor is 64 and the
modulation frequency is 64 x PWM frequency. The phase response
of the decimation filter for a 10-kHz PWM switching frequency
is shown. Typically, the PWM switching frequency is a decade above
the closed-loop bandwidth; therefore, the large-signal harmonic
will be typically less than l kHz.
For example, a 600-Hz-fundamental current waveform would have
a phase delay in the order of 30°. In some applications, this
phase delay may be unacceptable, in which case the Δ-Σ can be configured to sample the current waveform at a multiple
of the PWM frequency, and the phase delay can be reduced by the
oversampling factor. However, oversampling the current waveform
at a multiple of the PWM switching frequency will introduce additional
PWM harmonics into the passband. These harmonics can be removed
by a DSP with a notch filter.
Indeed, the integration of multiple Δ-Σ converters, a center-based PWM scheme, a 25-MIP DSP core, and
other peripherals such as encoder interfaces and event timers,
provides the motor-controller designer with a very powerful platform
to implement sophisticated control schemes which traditionally
would not have been at their disposal because of cost and design
constraints.
References
1. Murray, Aengus; Kettle, Paul; Moynihan, Finbarr; Margio, Alessandra,
Advances in DSP Based Motor Control Solutions, Intelligent Motion, Proceedings, June 1997.
2. AD7862 Datasheet, 10/96, Analog Devices Inc., Norwood, Mass., pp 14 to 15.
Simultaneous-Sampling ADCs
The current drawn by a motor can be split into two components--one
produces torque, and the other produces magnetic flux. For optimal
performance of the motor, these two components should be controlled
independently.
In conventional methods of controlling a three-phase motor, the
current (or voltage) supplied to the motor, and the frequency
of the drive, are the basic control variables. However, both the
torque and flux are functions of current (or voltage) and frequency.
This coupling effect can reduce the performance of the motor.
For example, if the torque is increased by increasing the frequency,
the flux tends to decrease.
Vector control of an ac motor involves controlling phase in addition
to drive and current frequency. Controlling the phase of the motor
requires feedback information on the position of the rotor relative
to the rotating magnetic field in the motor. Using this information,
a vector controller mathematically transforms the three-phase
drive currents into separate torque and flux components.
A typical dual-channel, simultaneous-sampling ADC (AD7862) for
vector-controller applications is shown in circuit (Fig. 2). Along with simultaneous-sampling capability, the high-speed,
low-power, 12-bit ADC has two 4-µs successive-approximation ADCs
and two track/hold amplifiers.
There are four analog inputs that are grouped into two channels
(A and B). Each channel has two inputs (VA1 and VA2, and VB1 and
VB2) that can be sampled simultaneously, thus preserving the relative
phase information of the signals on both analog inputs. The critical
track/hold specifications for preserving the relative phase information
are the -3-dB small-signal bandwidth (in this case, 3 MHz), aperture
delay (20 ns), aperture jitter (100 ps), and the aperture delay
matching (200 ps). Designed for motor-control applications, the
ADC under discussion also accepts bipolar analog input ranges
of ±10 V, ±2.5 V, and 0 to 2.5 V, while operating from a single
5-V supply.
The position of the field is derived by determining the current
in each phase of the motor. Only two phase currents need to be
measured as the third can be calculated if two phases are known.
Simultaneous sampling inputs VA1 and VA2 of the ADC are used to
digitize this information.
Simultaneous sampling is critical if the relative phase information
between the two channels is to be maintained. A current-sensing
isolation amplifier, transformer or Hall-effect sensor is used
between the motor and the ADC. Rotor information is estimated
from voltage measurements from two motor windings. The other two
simultaneous inputs of the ADC, VB1 and VB2, are used to obtain
this information. Once again, the relative phase of the two channels
is important. A DSP microprocessor is then used to perform the
mathematical transformations and control-loop calculations on
the information fed back by the ADC.
Sigma-Delta (Δ-Σ) ADCs
The Δ-Σ converters discussed in this section are part of a one-chip motor
control solution, the ADMC300, variations of which are available
from a number of manufacturers. Δ-Σ converter technology is based on an oversampling technique. The
input signal is typically sampled with a one-bit converter (a
modulator) at high frequencies, typically 1 to 2 MHz (Fig. 3). The resulting high-frequency bit stream is digitally filtered
and decimated (down sampled) to the effective sample rate.
This converter technology is well-suited to a bulk CMOS process,
and is also very conducive to mixed-signal integration. The Δ-Σ converter does, however, introduce additional system-level design
constraints that will be discussed later on in this article.
Typically, the sampling of a current waveform is synchronized
with the pulse-wave-modulated (PWM) waveform to reduce the effect
of PWM ripple on the sampled data. In doing so, each of the sideband
harmonics are symmetric about the PWM switching-frequency harmonic.
By sampling at the PWM switching frequency, all the sideband harmonics
sum to dc. By sampling at the zero mean point of the current ripple,
the sideband harmonics sum to zero. This point aligns with the
synchronization pulse of a center-based PWM system (Fig. 4). The frequency spectrum of a current waveform for a single-phase
system is shown. The figure depicts the fundamental, first, second,
third, and fourth PWM ripple harmonics.
With the Δ-Σ converter, the data is modulated (sampled) at 1 to 2 MHz. Therefore,
multiple harmonics of the PWM ripple are sampled. The Δ-Σ converter architecture that is part of the ADMC300 one-chip motor
control solution was analyzed to generate the spectrum of the
current waveform as well as the spectrum of the remodulated current
waveform, respectively.
It is apparent that the PWM harmonics are indeed sampled. However,
by choosing a modulation frequency equal to the decimation factor
times the PWM frequency, the sampled PWM harmonics are aliased
to dc. As is the case in the successive-approximation approach, the
PWM harmonic content of the original current waveform are not
present in the sampled spectrum.
The synchronizing of the modulation frequency with the PWM sample
frequency is key to the effective use of a Δ-Σ in a motor application. Not doing so would require the use of
antialiasing filters to remove the harmonic content before the
current information could be sampled. Typically, this synchronizing
is not an option with discrete implementations. However, with
the integration of a Δ-Σ converter and a PWM onto the one device (ADMC300), the necessary
sampling conditions can be satisfied.
A successive-approximation ADC is typically modeled as a finite
delay that is attributed to the conversion time of the particular
device. A Δ-Σ converter, on the other hand, is a dynamic system and must be
modeled as such.
In a motor-control application, these dynamic characteristics
have to be accounted for in the design of the control system.
Failing to account for the dynamics of the Δ-Σ converter in the feedback path of a closed-loop system will impact
the robustness of the resulting controller. Both the modulator
and decimator blocks exhibit a dynamic behavior. The dynamics
of the decimator portion, however, dominates the dynamic response
of the converter. The decimation filter is described as Figure 5.
where D denotes the decimation factor and G(z) is the transfer
function of the filter. The value "z" corresponds to a sampling
delay (i.e. for a set data samples x(0) ...x(n) ...where x(x)
is the most recent sample, then z x x(n) = x(n-1).
In the case of the ADMC300, the decimation factor is 64 and the
modulation frequency is 64 x PWM frequency. The phase response
of the decimation filter for a 10-kHz PWM switching frequency
is shown. Typically, the PWM switching frequency is a decade above
the closed-loop bandwidth; therefore, the large-signal harmonic
will be typically less than l kHz.
For example, a 600-Hz-fundamental current waveform would have
a phase delay in the order of 30°. In some applications, this
phase delay may be unacceptable, in which case the Δ-Σ can be configured to sample the current waveform at a multiple
of the PWM frequency, and the phase delay can be reduced by the
oversampling factor. However, oversampling the current waveform
at a multiple of the PWM switching frequency will introduce additional
PWM harmonics into the passband. These harmonics can be removed
by a DSP with a notch filter.
Indeed, the integration of multiple Δ-Σ converters, a center-based PWM scheme, a 25-MIP DSP core, and
other peripherals such as encoder interfaces and event timers,
provides the motor-controller designer with a very powerful platform
to implement sophisticated control schemes which traditionally
would not have been at their disposal because of cost and design
constraints.
References
1. Murray, Aengus; Kettle, Paul; Moynihan, Finbarr; Margio, Alessandra,
Advances in DSP Based Motor Control Solutions, Intelligent Motion, Proceedings, June 1997.
2. AD7862 Datasheet, 10/96, Analog Devices Inc., Norwood, Mass., pp 14 to 15.