To date, surface-mount packages, whether J-lead or gull wing, have been key enablers in the drive to reduce the overall size of electronic systems and devices. Despite the maturity of this technology however, increasing pressure to enhance reliability, increase functionality, and reduce size while lowering costs has kept researchers and designers permanently at the drawing board.
The current answers to these challenges are surface-mount (SMT), package options that can be loosely divided into two groups: ball-grid arrays (BGAs) and chip-scale packages (CSPs). While both of these technologies have been around for a number of years, their relatively high cost has relegated them to only the most space-constrained applications. Now, the pressure many designers face to reduce system dimensions has brought about a gradual migration toward these newer packages.
Unfortunately, other major obstacles to the adoption of these technologies still exist. The very nature of these packages means that reliability is questionable and that conventional testing and rework methods no longer apply. Also, the competitive nature of the high-end IC business is such that many package/IC houses are loathe to divulge the exact failure rates of their package design. As a result, mistakes will be repeated, thereby slowing progress. In addition, the plethora of package options causes some confusion for designers who must choose from among them. Their decision is further hampered by the limited time they have to perform extended reliability and performance testing, thanks to ever-present time-to-market pressure.
As a result of all this, the Jet Propulsion Laboratory (JPL), Pasadena, Calif., undertook the task of performing extended, independent, performance and reliability testing of SMT packages, using the two categories outlined above (regular SMT BGAs and CSPs). Working for NASA, JPL is one of the few facilities that can independently test the devices over a long period of time without time-to-market pressures. While still a work-in-progress, test results are available, along with information on lessons learned from the design, manufacturing, inspection, and reliability of these assemblies.
A review of the board-level reliability of CSP assembly and the projected values for specific environmental conditions were extracted from the data. These findings offer valuable information on package robustness, and provide a better understanding of the challenges associated with the implementation of SMT technology, particularly with the new, advanced, miniature CSPs.
Miniaturization Trends
SMT electronic packages are mounted directly onto the board surface, as opposed to the insertion of leads into plated through-holes (PTHs). While SMT come in several different package styles, they can generally be divided into two categories: those with terminations of leads on the periphery of the component on two or four sides, called peripheral-array packages (PAPs), and those with terminations (either pads or solder bumps) over much of the bottom of the component, called area-array packages (AAPs). PAPs have less potential for significant size reduction with increased I/O counts, compared to AAPs. The BGAs from the latter category are now the mainstay alternative to PAPs. For example, the CSP version of the two-sided PAP is the lead-on-chip (LOC) package, and the versions for AAPs are micro- (or mini-) BGA packages, which generally use eutectic solder balls.
Another level of miniaturization is accomplished by directly attaching the bare die to the printed wiring board (PWB). The direct flip-chip on board (FCOB) is the ultimate miniaturization level, achieving a die-to-PWB footprint ratio of nearly 70%. In FCOBs, solder bumps are permanently attached to the face of bare die, and the flip side is mounted on the PWB. In chip-on-board packages, with about 50% use-of-area efficiency, the pads of the wire-bonded die are used for second-level wire bonding onto the PWB.
Projections regarding the use of these packages are significantly different, with the numbers dependent on the market source. One projection from the British Packaging Association (BPA), U.K., is shown in Figure 1.
Several trends are apparent. The dual-in-line package (DIP) shows the most reduction in use, decreasing from 16 billion in 1996 to about five billion over 10 years (roughly one billion fewer per year). In contrast, the use of surface-mountable packages including quad flat packages (QFPs) is expected to increase in the next decade. The increase for plastic QFPs is forecast to be from seven to 18 billion within the first five years, and will almost plateau with an increase of only two billion for another five years. Within 10 years, the flip-chip-on-board package (FCOB) is forecast to increase from five to 13 billion.
The rate of increase in the use of CSP and flip-chip packages is the same. Both are projected to reach up to six billion production units by the year 2006. In contrast, the expected increase for BGAs for the next 10 years is minimal, reaching a total production demand of only 1.5 billion. The projection for BGAs suggests that these packages were only an interim solution, that the devices are a stepping stone for the industry's wider acceptance of flip-chip and chip-scale packages that better meet the demands for denser and lighter miniaturized applications.
To date, surface-mount packages, whether J-lead or gull wing, have been key enablers in the drive to reduce the overall size of electronic systems and devices. Despite the maturity of this technology however, increasing pressure to enhance reliability, increase functionality, and reduce size while lowering costs has kept researchers and designers permanently at the drawing board.
The current answers to these challenges are surface-mount (SMT), package options that can be loosely divided into two groups: ball-grid arrays (BGAs) and chip-scale packages (CSPs). While both of these technologies have been around for a number of years, their relatively high cost has relegated them to only the most space-constrained applications. Now, the pressure many designers face to reduce system dimensions has brought about a gradual migration toward these newer packages.
Unfortunately, other major obstacles to the adoption of these technologies still exist. The very nature of these packages means that reliability is questionable and that conventional testing and rework methods no longer apply. Also, the competitive nature of the high-end IC business is such that many package/IC houses are loathe to divulge the exact failure rates of their package design. As a result, mistakes will be repeated, thereby slowing progress. In addition, the plethora of package options causes some confusion for designers who must choose from among them. Their decision is further hampered by the limited time they have to perform extended reliability and performance testing, thanks to ever-present time-to-market pressure.
As a result of all this, the Jet Propulsion Laboratory (JPL), Pasadena, Calif., undertook the task of performing extended, independent, performance and reliability testing of SMT packages, using the two categories outlined above (regular SMT BGAs and CSPs). Working for NASA, JPL is one of the few facilities that can independently test the devices over a long period of time without time-to-market pressures. While still a work-in-progress, test results are available, along with information on lessons learned from the design, manufacturing, inspection, and reliability of these assemblies.
A review of the board-level reliability of CSP assembly and the projected values for specific environmental conditions were extracted from the data. These findings offer valuable information on package robustness, and provide a better understanding of the challenges associated with the implementation of SMT technology, particularly with the new, advanced, miniature CSPs.
Miniaturization Trends
SMT electronic packages are mounted directly onto the board surface, as opposed to the insertion of leads into plated through-holes (PTHs). While SMT come in several different package styles, they can generally be divided into two categories: those with terminations of leads on the periphery of the component on two or four sides, called peripheral-array packages (PAPs), and those with terminations (either pads or solder bumps) over much of the bottom of the component, called area-array packages (AAPs). PAPs have less potential for significant size reduction with increased I/O counts, compared to AAPs. The BGAs from the latter category are now the mainstay alternative to PAPs. For example, the CSP version of the two-sided PAP is the lead-on-chip (LOC) package, and the versions for AAPs are micro- (or mini-) BGA packages, which generally use eutectic solder balls.
Another level of miniaturization is accomplished by directly attaching the bare die to the printed wiring board (PWB). The direct flip-chip on board (FCOB) is the ultimate miniaturization level, achieving a die-to-PWB footprint ratio of nearly 70%. In FCOBs, solder bumps are permanently attached to the face of bare die, and the flip side is mounted on the PWB. In chip-on-board packages, with about 50% use-of-area efficiency, the pads of the wire-bonded die are used for second-level wire bonding onto the PWB.
Projections regarding the use of these packages are significantly different, with the numbers dependent on the market source. One projection from the British Packaging Association (BPA), U.K., is shown in Figure 1.
Several trends are apparent. The dual-in-line package (DIP) shows the most reduction in use, decreasing from 16 billion in 1996 to about five billion over 10 years (roughly one billion fewer per year). In contrast, the use of surface-mountable packages including quad flat packages (QFPs) is expected to increase in the next decade. The increase for plastic QFPs is forecast to be from seven to 18 billion within the first five years, and will almost plateau with an increase of only two billion for another five years. Within 10 years, the flip-chip-on-board package (FCOB) is forecast to increase from five to 13 billion.
The rate of increase in the use of CSP and flip-chip packages is the same. Both are projected to reach up to six billion production units by the year 2006. In contrast, the expected increase for BGAs for the next 10 years is minimal, reaching a total production demand of only 1.5 billion. The projection for BGAs suggests that these packages were only an interim solution, that the devices are a stepping stone for the industry's wider acceptance of flip-chip and chip-scale packages that better meet the demands for denser and lighter miniaturized applications.