Collective Design Advances IC Packaging

The semiconductor industry has experienced dramatic growth and technological advancement over the past several years. What was "leading edge" in 1994, with transistor features in the 0.5-µm range, gave way to even greater challenges just three years later, as the industry approached 0.25-µm technology.

This growth and development is in direct response to applications like electronic data processing, electronic games and toys, stereos, cellular phones and pagers, switching systems and satellites, military/aerospace, industrial, and automotive products. Each of these applications has specific IC-packaging needs, which has resulted in a plethora of options, ranging from low-cost, quad flat packages (QFPs) to expensive, high-performance multichip modules (MCMs).

While evaluating the various packaging alternatives, the designer must consider to what level that package is supported by the various pc-board manufacturers. On their side, many strides have been made as far as via size, line width, and spacing are concerned. Until recently, the IC-design and pc-board manufacturing industries worked independently. Now, rising levels of integration make it imperative that IC designers, package manufacturers, and the pc-board community work closely to reduce overall cost, enhance performance, and ensure the feasibility and manufacturability of the final design.

To that end, a number of technology roadmaps have been outlined to define the challenges ahead for the industry. The overall goal of these roadmaps is to encourage participants, at every level, to cooperate and realize each other's full potential to their benefit and the benefit of the end user.

Package Requirements
The main issues driving component packaging today are thermal and electrical performance, real-estate constraints, and cost. The applications and systems typically dictate what's needed, with suppliers moving quickly in response to ever-shrinking time-to-market windows (Fig. 1).

The high-end microprocessors run at higher frequencies, and require thermally and electrically enhanced packages. These thermal enhancements come in the form of thermal vias, heat slugs, heat sinks, and component towers, while the electrical enhancements are usually provided through multilayer packages and in-package, capacitance-control features. Hermetic ceramic packages are popular for these applications.

For mid-range systems, performance is important, but so is cost. Therefore, thermally enhanced multilayer packages such as plastic ball-grid arrays (PBGAs) or QFPs are possible candidates.

For low-end and portable systems, cost and form factor are critical. Generally, surface-mount packages, such as QFPs, thin small-outline packages (TSOPs), and tape-automated bonding (TAB) technologies are used. The ideal component package is rarely obvious, however.

For many, the robust assembly capability of the BGA, which has I/Os situated underneath the package body, provides greater system capability than the QFP (Fig. 2). Also against the QFP is the fact that its I/O-count capabilities top out at 208, as anything in excess can stress the package's peripheral-lead arrangement. Yet, both the QFP and BGA can be thermally enhanced, allowing their use in a greater range of applications.

Increasing functionality and speed requires more power, more bond pads on the die, and more pins on the package. Fortunately, even with the increase in bonding sites, the I/O count in many packages is kept to a minimum through the use of decoupling capacitors within the package and on the die. Adding power and ground planes within the package further reduces the number of I/Os. In enhanced plastic packages, I/O counts may be higher to avoid adding extra layers, thus in-package capacitance is generally not feasible. For example, a microprocessor that has 168 I/Os in a ceramic package might require 196 I/Os in a plastic surface-mount package. Such conditions make the package characteristics very important to both the designer and the assembler.

During the 1960s, IBM and Delco practiced a totally non-packaged IC assembly method called flip-chip. This technology, which has risen in popularity as of late, places solder bumps, or connections, on the component bonding site, with the package attached to the substrate in a face-down fashion.

Known Good Die
The use of "known-good die," coupled with the determination that a die designed for wire bonding could be easily converted to an array format, has provided a new format that promises to provide the performance and thermal characterization needed by the industry--but in a die-sized package. One variation of these packages is the mini-BGA (Fig. 3). Many manufacturers throughout the world, including Hitachi and Intel, have licensed this design, which was standardized by the Joint Electron Device Engineering Council (JEDEC).

The mini-BGA is constructed using a flexible circuit, similar to TAB circuitry. The flex circuit is attached to the surface of an IC using a semiconductor-grade elastometer; its structure forms the basic redistribution layer or interposer. Flexible, ribbon-like bond leads of metal, such as gold or gold-plated copper or nickel, are bonded directly to the gold or aluminum pads of the IC. This allows a chip to be used in a QFP, where it is wire-bonded to a lead frame. It also could be repackaged in the smaller CSP configuration by having the interposer convert the peripheral bonding sites of the die to an array configuration.

The elastometer, or compliant polymer layer, serves to decouple the differential expansion of the silicon from that of the interconnecting substrate. This compliant layer, together with the S-shaped bond lead ribbon, effectively decouples the device from the strains of thermal expansion. The result is chip-size packages that are compliant in the x, y, and z directions. In addition, this facilitates testing and assembly, while enhancing reliability. Although Figure 3 shows just a single metal-layer construction, mini-BGAs can be fabricated with two metal layers for power and ground distribution, and with controlled impedance, making them suitable for the highest-level of electrical performance.

Application-Specific ICs
The most apparent advance in the semiconductor industry was the development of application-specific integrated circuits (ASICs). Higher clock rates, both on and off the chip, provided not only greater capability, but also greater challenges. To buffer increases in chip speed, new materials are being researched for wafer-level interconnections (as evidenced by the announcement from IBM and others to use copper wiring instead of aluminum). These advances may also have implications at the chip-to-substrate interconnect level.

The semiconductor industry has experienced dramatic growth and technological advancement over the past several years. What was "leading edge" in 1994, with transistor features in the 0.5-µm range, gave way to even greater challenges just three years later, as the industry approached 0.25-µm technology.

This growth and development is in direct response to applications like electronic data processing, electronic games and toys, stereos, cellular phones and pagers, switching systems and satellites, military/aerospace, industrial, and automotive products. Each of these applications has specific IC-packaging needs, which has resulted in a plethora of options, ranging from low-cost, quad flat packages (QFPs) to expensive, high-performance multichip modules (MCMs).

While evaluating the various packaging alternatives, the designer must consider to what level that package is supported by the various pc-board manufacturers. On their side, many strides have been made as far as via size, line width, and spacing are concerned. Until recently, the IC-design and pc-board manufacturing industries worked independently. Now, rising levels of integration make it imperative that IC designers, package manufacturers, and the pc-board community work closely to reduce overall cost, enhance performance, and ensure the feasibility and manufacturability of the final design.

To that end, a number of technology roadmaps have been outlined to define the challenges ahead for the industry. The overall goal of these roadmaps is to encourage participants, at every level, to cooperate and realize each other's full potential to their benefit and the benefit of the end user.

Package Requirements
The main issues driving component packaging today are thermal and electrical performance, real-estate constraints, and cost. The applications and systems typically dictate what's needed, with suppliers moving quickly in response to ever-shrinking time-to-market windows (Fig. 1).

The high-end microprocessors run at higher frequencies, and require thermally and electrically enhanced packages. These thermal enhancements come in the form of thermal vias, heat slugs, heat sinks, and component towers, while the electrical enhancements are usually provided through multilayer packages and in-package, capacitance-control features. Hermetic ceramic packages are popular for these applications.

For mid-range systems, performance is important, but so is cost. Therefore, thermally enhanced multilayer packages such as plastic ball-grid arrays (PBGAs) or QFPs are possible candidates.

For low-end and portable systems, cost and form factor are critical. Generally, surface-mount packages, such as QFPs, thin small-outline packages (TSOPs), and tape-automated bonding (TAB) technologies are used. The ideal component package is rarely obvious, however.

For many, the robust assembly capability of the BGA, which has I/Os situated underneath the package body, provides greater system capability than the QFP (Fig. 2). Also against the QFP is the fact that its I/O-count capabilities top out at 208, as anything in excess can stress the package's peripheral-lead arrangement. Yet, both the QFP and BGA can be thermally enhanced, allowing their use in a greater range of applications.

Increasing functionality and speed requires more power, more bond pads on the die, and more pins on the package. Fortunately, even with the increase in bonding sites, the I/O count in many packages is kept to a minimum through the use of decoupling capacitors within the package and on the die. Adding power and ground planes within the package further reduces the number of I/Os. In enhanced plastic packages, I/O counts may be higher to avoid adding extra layers, thus in-package capacitance is generally not feasible. For example, a microprocessor that has 168 I/Os in a ceramic package might require 196 I/Os in a plastic surface-mount package. Such conditions make the package characteristics very important to both the designer and the assembler.

During the 1960s, IBM and Delco practiced a totally non-packaged IC assembly method called flip-chip. This technology, which has risen in popularity as of late, places solder bumps, or connections, on the component bonding site, with the package attached to the substrate in a face-down fashion.

Known Good Die
The use of "known-good die," coupled with the determination that a die designed for wire bonding could be easily converted to an array format, has provided a new format that promises to provide the performance and thermal characterization needed by the industry--but in a die-sized package. One variation of these packages is the mini-BGA (Fig. 3). Many manufacturers throughout the world, including Hitachi and Intel, have licensed this design, which was standardized by the Joint Electron Device Engineering Council (JEDEC).

The mini-BGA is constructed using a flexible circuit, similar to TAB circuitry. The flex circuit is attached to the surface of an IC using a semiconductor-grade elastometer; its structure forms the basic redistribution layer or interposer. Flexible, ribbon-like bond leads of metal, such as gold or gold-plated copper or nickel, are bonded directly to the gold or aluminum pads of the IC. This allows a chip to be used in a QFP, where it is wire-bonded to a lead frame. It also could be repackaged in the smaller CSP configuration by having the interposer convert the peripheral bonding sites of the die to an array configuration.

The elastometer, or compliant polymer layer, serves to decouple the differential expansion of the silicon from that of the interconnecting substrate. This compliant layer, together with the S-shaped bond lead ribbon, effectively decouples the device from the strains of thermal expansion. The result is chip-size packages that are compliant in the x, y, and z directions. In addition, this facilitates testing and assembly, while enhancing reliability. Although Figure 3 shows just a single metal-layer construction, mini-BGAs can be fabricated with two metal layers for power and ground distribution, and with controlled impedance, making them suitable for the highest-level of electrical performance.

Application-Specific ICs
The most apparent advance in the semiconductor industry was the development of application-specific integrated circuits (ASICs). Higher clock rates, both on and off the chip, provided not only greater capability, but also greater challenges. To buffer increases in chip speed, new materials are being researched for wafer-level interconnections (as evidenced by the announcement from IBM and others to use copper wiring instead of aluminum). These advances may also have implications at the chip-to-substrate interconnect level.