Over the past few years, die stacking has emerged as a powerful tool for satisfying challenging IC packaging requirements. Integrating chips vertically in a single package multiplies the amount of silicon that can be crammed in a given package footprint, conserving pc-board real estate. At the same time, it enables shorter routing of interconnects from chip to chip, which speeds signalling between them. Another benefit is the simplification of surface-mount pc-board assembly because fewer components must be placed on the board.
Initial applications of die stacking, also called chip stacking, were two-chip memory combinations such as flash and SRAM. Even today, memory stacks remain popular and include new variations like flash plus flash. But chip stacking has been extended beyond memories to logic and analog ICs in packages that may also contain surface-mount passives.
In addition, chip stacking has evolved to include three- or four-die stacks and side-by-side combinations of stacked and unstacked dies within a package. The dies are typically mounted to a substrate, which is bumped to create either a chip scale package (CSP) or ball grid array (BGA) as the final package.
Though chip stacking began with mounting smaller dies onto larger ones to enable wirebonding of both, packaging vendors have developed techniques for stacking same-size die or for stacking a larger die on top of a smaller one. These variations have helped expand the number of stacked-die package options, creating whole portfolios of what vendors commonly call 3-D packages. A variety of these are now in high-volume production (Fig. 1).
Depending on the level of functional integration, 3-D packages may also be classified as systems-in-packages (SIPs). Using chip stacking to build SIPs can dramatically reduce the footprint of an unstacked, multichip design and enhance electrical performance.
A design example provided by Advanced Semiconductor Engineering (ASE) illustrates the mechanical and electrical advantages of converting a Mini-PC card with 2.4-GHz RF, logic, and DSP chips to a stacked-die multichip module in a BGA. The Mini-PC card design occupies an area of 3225 mm2 versus just 729 mm2 for the stacked-chip BGA. Plus, due to the reductions in interconnect path from logic to DSP, the crosstalk, delay, and inductance control are all improved dramatically (Fig. 2).
The viability of stacked-die packaging greatly depends on the availability of known good die (KGD). That's because the stacked-die packages' manufacturing yields will be a function of the yields of the die being packaged. Naturally, if yields are low, cost will be high. For semiconductor package assembly companies that manufacture stacked-die packages, a critical issue is whether the KGDs can be obtained in wafer form.
The package manufacturers need the die in wafer form so they can thin the wafers (through backgrinding and polishing) to the very shallow thicknesses (several mils) required for die stacking. Therefore, the chip-stacking process must begin with either high-yielding wafers, or those that have been supplied with a wafer map identifying the bad dies, so they may be discarded.
For some devices, like lower-capacity NOR flash memory, it's possible to obtain KGDs in a wafer. But for other chips, KGDs aren't readily available at the wafer level. Examples include SDRAM, DSPs, and baseband processors. Often these die are large, expensive, and difficult to source. So the economics of integrating them within stacked-die packages aren't good. For these reasons, semiconductor packaging companies have been developing an alternative form of 3-D integration, package stacking, that eliminates KGD concerns and provides another path to SIP.
Underlying Technologies: Advances in chip-stacking techniques are enabling the stacking of more dies within a package of a given height, while also placing the same number of dies into a lower-profile package. To accomplish these basic goals, packaging companies must develop a variety of underlying technologies. In terms of die processing, the key elements are wafer thinning, thin-wafer handling, and thin-die attach.
Nevertheless, chip stacking imposes special requirements on wirebonding and flip-chip assembly as well. At the package level, there's a need to source and develop thin substrates and low-profile, fine-pitch BGAs too.
Wafer thinning involves a combination of traditional backgrinding with a polishing step to remove the stresses put into the chip during backgrinding. These techniques currently produce dies that are just 100 to 150 µm thick, depending on the vendor and the wafer size. Amkor Technology and ChipPAC are both thinning 200-mm diameter wafers to the 100-µm level, while ASE is achieving 140 µm on these wafers. Meanwhile, ChipPAC also thins 300-mm diameter wafers to 150 µm thick in production.
But the future of die stacking lies with even thinner wafers. ChipPac and ASE expect to produce 200-mm wafers with 75-µm thicknesses by the end of the year, while Amkor forecasts 300-mm wafers in 76-µm thickness. Moreover, both ChipPAC and Amkor indicate that 50-µm wafers will be ready by the end of next year for 300-mm wafers.