How High A Stack? From a technical point of view, just how many dies can be stacked depends on the thickness of the final package and the thickness of each layer within the package. These include the substrate, die, spacers (if required), and BGA ball diameter. Substrate thickness is in turn influenced by the number of chip I/Os, which determines the number of substrate layers necessary. BGA ball diameter follows BGA ball pitch. As a result, ball diameter ranges from 0.75 mm for 1.27-mm pitch down to 0.2 mm for the extreme 0.35-mm pitch.
BGA packages come in a range of sizes. Package heights could even be 2.23 mm for a standard BGA, though much thinner profiles became common for portable applications like cell phones. In the past, 1.4 mm was the standard for stacked-chip packages in these applications. Now demand is shifting to 1.2- and 1.0-mm high packages, and even 0.8 mm is a possibility.
As a ballpark figure, it's currently possible to build three- and four-die stacks in 1.4-mm packages. As die thickness decreases to 50 µm, that number could increase. Yet as the number of dies increases, the yield decreases. Then again, it also is difficult to source KGD. These are two major motivations for package stacking.
While package stacking increases material costs per package and overall package height, it provides higher yields per stacked device, which lowers cost. According to DPAC Technologies, which offers package stacking but not die stacking, the use of known-good packaged devices leads to manufacturing yields in excess of 97%. The company has stacked as many as eight packages in a single device. But over 95% of its demand is for two-chip stacks.
In general, package stacking becomes a more attractive alternative to die stacking as the number of die and cost per die increase. But ultimately, application specifics will determine whether package stacking holds greater benefits than die stacking. One vendor, Amkor Technology, which offers die and package stacking, has developed a total-cost estimation tool that evaluates the two approaches based on die cost and yield, package cost and yield, and test inputs.
In memory applications, package stacking can also be used to obtain the desired capacity at a reasonable cost. Kevin Perry, vice president of sales and marketing at DPAC Technologies, cites a memory module for a server. Presently, a standard DIMM holds 18 512-Mbit SDRAM chips for a maximum of 1 Gbyte. Consider some hypothetical price comparisons that would justify chip stacking.
Assume that a 512-Mbit SDRAM sells for approximately $75 to $100 per chip, while a 256-Mbit SDRAM runs about $12. If stacking two 256-Mbit ICs costs around $6 to $8, then a two-chip stack equivalent of a 512-Mbit chip would be about $30. Consequently, building the 1-Gbyte DIMM with stacked 256-Mbit chips would effectively save $45 to $70 per 512-Mbit chip.
Thermal issues are another reason for package stacking. In the past, graphics processors and memories have been integrated within multichip modules. But lately, the processor's power dissipation has risen to 3 W or higher, making it necessary to heatsink the chip. That requirement complicates attempts to stack processor and memory chips.
On the other hand, graphics processors come in thermally enhanced packages that lend themselves to package stacking. Moreover, the DRAM or graphics RAM meant to be stacked with the processor probably isn't available as KGD at the wafer level, while known-good packaged versions are around.
Package stacking needs thin, flat, high-temperature, moisture-resistant packages to handle the multiple reflows and rework associated with SMT. So far, it has been applied in production only to leadframe packages like TSOPs. However, vendors like Amkor have been developing processes to stack CSPs and BGAs to achieve higher I/O counts. Amkor is currently qualifying a package-stacking process based on its etCSP package (Fig. 4). Production of the new process is expected next year. Future applications of etCSP may combine die stacking with package stacking.
Meanwhile, DPAC Technologies' CS-Stack technology stacks two fine-pitch ball grid arrays (FBGAs). The FBGA addresses both the electrical and mechanical requirements of advanced SDRAM and DDR SDRAM. As FBGA-packaged DDR memories start to become available in the next six to nine months, DPAC expects to begin production of CS-Stack components.