Figure 3, an application circuit adapted from the National datasheet, shows a Zener bridge (BR1) across the output of the old triac controller. A “valley-fill” circuit follows the bridge. The network of diodes and capacitors between D3 and C10 constitutes one possible configuration for such a circuit. Valley fill allows the buck regulator in the chip to draw power even while the triac is in cutoff. This allows a smaller capacitance for C10, adds passive PFC, and eliminates some 120-Hz flicker.
In operation, the chip senses the rectified line voltage at pin 10 (BLDR). The “bleeder” terminology means this is the node at which the circuit emulates the resistance of an incandescent bulb. That is, resistor R5 maintains IH.
Also at pin 10, the schematic shows an external series-pass regulator comprising R2, D1, and Q1. D1 is typically a 15-V Zener. It forces Q1 to “stand off ” most of the rectified line voltage. Note that there’s no capacitance on Q1’s source. This means the voltage on the sensing pin can rise and fall with the rectified line voltage as the line voltage drops below D1’s Zener voltage. To provide a steady voltage on the main power pin, a diode-capacitor network (D2, C5) keeps that node up while the voltage on the bleeder pin goes low.
FIRING ANGLE TO PWM
National’s design provides a 10% to 100% dimming range, based on triac-dimmer firing angles between 45° and 135° of the ac line waveform. Inside the chip, a ramp generator produces a 5.85-kHz sawtooth wave with a level between 1 and 3 V. The sawtooth is placed on Pin 1 (ASNS), where it’s filtered by R1 and C3 and applied to Pin 2 (FLTR1). Back inside the chip, the signal on FLTR1 is compared to the output of a ramp signal.
The ramp comparator’s output is a series of pulses whose on-time is inversely proportional to the average voltage level at FLTR1. Because the FLTR1 signal can vary between 0 and 4 V (the limits of the sawtooth on the ASNS pin), and the ramp only swings between 1 and 3 V, the ramp comparator’s output will be on whenever the FLTR1 voltage is below 1 V and off when it is above 3 V.
The ramp comparator’s output drives a common-source N-channel MOSFET through a Schmitt trigger. (The comparator output also appears on Pin 3, (DIM), which is used in a scheme to gang multiple LM3445 chips.) The MOSFET inverts the ramp comparator’s output, and its output voltage directly controls the peak current that will be delivered by Q2 during its on-time.
The MOSFET’s drain voltage is proportional to the duty cycle of the triac dimmer. The amplitude of the ramp causes this proportionality to “hard limit” for duty cycles above 75% and below 25%. To reduce ripple in this signal, the chip provides for a second, one-pole, 10-Hz low-pass filter stage that comprises C4 on pin 5 (FLTR2) and an internal 370-kO resistor.
Pin 4 (COFF) is used with C11 for setting PWM off time. Pin 5 (FLTR2) is the input to the second filter for the LED current control voltage. Capacitor C4 filters the PWM dimming signal to supply that dc voltage. Finally, maximum LED current is set via pin 7 (ISNS) by means of R3 at the source of the switching MOSFET Q2.
That describes one way to do the job monolithically. If you’re looking at a special case, you may want to tackle the job with a custom design. Companies that can help you include Texas Instruments (search www.ti.com for “dimming”) and Microchip.