Part 1 of this article appeared in our Analog Supplement, Nov. 20, 2000, p. 23.
Temperature can accelerate the physico-chemical factors that influence numerous failure mechanisms in electronic components. By varying temperature appropriately, it's possible to accelerate life-testing methods to screen electronic components and weed out infant-mortality cases. This article uncovers the path to good thermal design.
Thermal overstress effects can be quite dramatic on both components and pc boards. Photographs bring home this point. The charring of a bipolar junction transistor due to thermal overstress caused by electrical overstress (EOS) is shown in Figure 1. When a device is subjected to more than its rated current or voltage and it exceeds the power dissipation defined by its safe operating area, EOS occurs. Another example of EOS-induced thermal overstress is revealed in Figure 2. Electrostatic discharge (ESD) can cause thermal overstress, too (Fig. 3).
Accelerated testing provides information about the lifetime distribution of a component within a compressed time-frame, thereby reducing the cost of testing. With semiconductor devices, accelerated testing is implemented by applying temperature cycling or other stressing factors. In addition to providing information on the life expectancy of the device, the testing exposes latent defects. Data from accelerated tests helps predict the reliability of components.
Accelerated tests use temperatures in the 75°C to 225°C range and humidity in the 50% to 90% range, depending on the failure mechanisms and category of device. A standard combination is 85°C with 85% relative humidity. Accelerated testing stimulates failure mechanisms, such as internal corrosion and metallic growth due to ion migration.
Tests that apply environmental stresses in addition to temperature are known as Highly Accelerated Stress Tests (HAST). A number of models, such as the Arrhenius model (which was explained in Part 1 of this article), the Eyring model, the Reich-Hakim model, the Peck model, and the Lawson model, are used to represent accelerated life-testing on electronic components.
The main objective of any screening technique is to accelerate the failure mechanisms and processes so that weak products—those that have intrinsic faults such as manufacturing defects—fail during testing. This eliminates the infant-mortality cases. Products that pass the screening test are regarded as being in their "useful life" phase of the familiar bathtub curve (Fig. 4).
A widely implemented screening technique is Environmental Stress Screening (ESS). In this procedure, environmental stresses are applied in an accelerated manner to force the failure of defective products. For electronic components that have a long, productive operating life, this technique is useful to screen components. Devices that survive ESS tests will perform well during their useful life phase until wear-out failure occurs.
Stresses used for ESS screening include random vibration, temperature cycling, thermal shock, high temperature, and electrical stimuli. A good ESS screen, as established by experience, constitutes the cyclic application of various temperatures at different rates for a specific number of times, with dwell times at different temperatures. Customized ESS screens, however, can be designed to reflect the operating environment in which the component has to work.
In ESS, subjecting the product to very high and very low temperatures at a fast rate accelerates failure mechanisms. The rapid temperature change creates stresses in the product due to the different thermal coefficients of expansion for the materials used. Plus, it triggers temperature-dependent failure mechanisms. The rate of temperature change is about 5°C to 10°C per minute between 10°C to 70°C, with a dwell time at each temperature limit of around 30 minutes.
Component-Level Screening Methods
Before qualifying for use in high-reliability systems, components undergo three major types of testing: environmental, physical, and electrical characteristics. The widely used MIL-STD 202F outlines the involved test procedures. For electronic components, the burn-in standards are based on MIL-STD-883, MIL-STD-750, and MIL-STD-S-19500.
The salient features of the tests related to thermal effects are:
High-temperature burn-in. For burn-in testing, the device is subjected to temperature stress in the range for which it's rated—that is, 70°C for commercial devices and 125°C for military de-vices—for a duration ranging from 24 to 168 hours. The device is tested functionally by powering it up and applying test patterns so the testing is dynamic. The purpose here is to eliminate marginal devices that have manufacturing defects, including wire-bond defects, oxide-layer faults, and metallization defects. After burn-in testing, the component is tested electrically to determine whether its parameters have degraded and to study its characteristics. Burn-in testing at the device level is more economical than at the card or system level.
Temperature cycling. Exposing the devices to alternating periods of low and high temperature brings out defects like poor wire bonds, die-substrate attachment problems, cracks in the die, mismatch in the thermal coefficients of expansion from different construction materials, seal defects, and defects in the plastic packages. The temperature limits for cycling devices lie in the region of 40°C to 125°C or 65°C to 150°C, depending on the category of the device (industrial or military). The recommended number of cycles is 20 (at least 10). At temperature extremes, the dwell time should be at least 10 minutes. After cycling, the temperature is brought down to 25°C, and the device's electrical parameters are measured and compared with its rated specifications.
Part 1 of this article appeared in our Analog Supplement, Nov. 20, 2000, p. 23.
Temperature can accelerate the physico-chemical factors that influence numerous failure mechanisms in electronic components. By varying temperature appropriately, it's possible to accelerate life-testing methods to screen electronic components and weed out infant-mortality cases. This article uncovers the path to good thermal design.
Thermal overstress effects can be quite dramatic on both components and pc boards. Photographs bring home this point. The charring of a bipolar junction transistor due to thermal overstress caused by electrical overstress (EOS) is shown in Figure 1. When a device is subjected to more than its rated current or voltage and it exceeds the power dissipation defined by its safe operating area, EOS occurs. Another example of EOS-induced thermal overstress is revealed in Figure 2. Electrostatic discharge (ESD) can cause thermal overstress, too (Fig. 3).
Accelerated testing provides information about the lifetime distribution of a component within a compressed time-frame, thereby reducing the cost of testing. With semiconductor devices, accelerated testing is implemented by applying temperature cycling or other stressing factors. In addition to providing information on the life expectancy of the device, the testing exposes latent defects. Data from accelerated tests helps predict the reliability of components.
Accelerated tests use temperatures in the 75°C to 225°C range and humidity in the 50% to 90% range, depending on the failure mechanisms and category of device. A standard combination is 85°C with 85% relative humidity. Accelerated testing stimulates failure mechanisms, such as internal corrosion and metallic growth due to ion migration.
Tests that apply environmental stresses in addition to temperature are known as Highly Accelerated Stress Tests (HAST). A number of models, such as the Arrhenius model (which was explained in Part 1 of this article), the Eyring model, the Reich-Hakim model, the Peck model, and the Lawson model, are used to represent accelerated life-testing on electronic components.
The main objective of any screening technique is to accelerate the failure mechanisms and processes so that weak products—those that have intrinsic faults such as manufacturing defects—fail during testing. This eliminates the infant-mortality cases. Products that pass the screening test are regarded as being in their "useful life" phase of the familiar bathtub curve (Fig. 4).
A widely implemented screening technique is Environmental Stress Screening (ESS). In this procedure, environmental stresses are applied in an accelerated manner to force the failure of defective products. For electronic components that have a long, productive operating life, this technique is useful to screen components. Devices that survive ESS tests will perform well during their useful life phase until wear-out failure occurs.
Stresses used for ESS screening include random vibration, temperature cycling, thermal shock, high temperature, and electrical stimuli. A good ESS screen, as established by experience, constitutes the cyclic application of various temperatures at different rates for a specific number of times, with dwell times at different temperatures. Customized ESS screens, however, can be designed to reflect the operating environment in which the component has to work.
In ESS, subjecting the product to very high and very low temperatures at a fast rate accelerates failure mechanisms. The rapid temperature change creates stresses in the product due to the different thermal coefficients of expansion for the materials used. Plus, it triggers temperature-dependent failure mechanisms. The rate of temperature change is about 5°C to 10°C per minute between 10°C to 70°C, with a dwell time at each temperature limit of around 30 minutes.
Component-Level Screening Methods
Before qualifying for use in high-reliability systems, components undergo three major types of testing: environmental, physical, and electrical characteristics. The widely used MIL-STD 202F outlines the involved test procedures. For electronic components, the burn-in standards are based on MIL-STD-883, MIL-STD-750, and MIL-STD-S-19500.
The salient features of the tests related to thermal effects are:
High-temperature burn-in. For burn-in testing, the device is subjected to temperature stress in the range for which it's rated—that is, 70°C for commercial devices and 125°C for military de-vices—for a duration ranging from 24 to 168 hours. The device is tested functionally by powering it up and applying test patterns so the testing is dynamic. The purpose here is to eliminate marginal devices that have manufacturing defects, including wire-bond defects, oxide-layer faults, and metallization defects. After burn-in testing, the component is tested electrically to determine whether its parameters have degraded and to study its characteristics. Burn-in testing at the device level is more economical than at the card or system level.
Temperature cycling. Exposing the devices to alternating periods of low and high temperature brings out defects like poor wire bonds, die-substrate attachment problems, cracks in the die, mismatch in the thermal coefficients of expansion from different construction materials, seal defects, and defects in the plastic packages. The temperature limits for cycling devices lie in the region of 40°C to 125°C or 65°C to 150°C, depending on the category of the device (industrial or military). The recommended number of cycles is 20 (at least 10). At temperature extremes, the dwell time should be at least 10 minutes. After cycling, the temperature is brought down to 25°C, and the device's electrical parameters are measured and compared with its rated specifications.