How much can one package
take? As consumer electronics
design features scale down to
45-nm and even 32-nm nodes,
IC makers are pushed to the
limits to shoehorn more functionality
into these packages-
and lest we not forget
the even thornier interconnection issues.
The logical approach is packaging in the Z direction,
or 3D IC packaging. In the meantime, IC makers
try to satisfy consumer demands with advanced
methods for tried-and-true wire-bonding technology
while looking ahead at flip-chip and wafer-chip
bonding using through-silicon vias (TSVs).
The quest for denser 3D IC packaging spreads
across a spectrum of companies. Amkor, IBM,
IMEC, Intel, Qimonda AG, Samsung, STATS
ChipPAC, Tessera, Texas Instruments, Tezzaron,
Xanoptix, Ziptronix, and ZyCube are all investigating
3D IC packages. Some are also sampling 3D
ICs using TSV technology.
For instance, Amkor Technology Inc., a provider
of advanced semiconductor assembly and test services,
and IMEC, a nonprofit nanoelectronics and
nanotechnology research center based in Belgium,
entered into a two-year collaboration agreement to
develop cost-effective 3D integration technology. It
will be based on wafer-level processing techniques.
Market research firm Yolé Dévelopment foresees
a number of 2D and 3D technologies that will
coexist, depending on the required packaging density.
The firm also expects TSV technology to dominate
future high-density packaging. According to the company, TSV technology first will be used
for packaging memories, followed by adding
logic and then control devices in the form of
ASICs and system-on-a-chip (SoC) ICs.
Stacking continues to be popular, with advances coming at
the chip, wafer, and package levels. Two of the hottest packaging
trends are the use of package-on-package (PoP) and multichip
package (MCP) methods. Chips with lower yields appear
to favor PoPs, but those with high density and performance levels
favor MCPs. Another percolating area revolves around system-
in-package (SiP) technology, where logic and memory
devices are manufactured in their own respective processes and
then joined together in an SiP package.
Memory technology likely will be the first to fully utilize
TSVs on a production basis. Samsung Electronics Co. Ltd. has
crafted an all-DRAM stacked-memory package using waferscale-
package (WSP) TSVs housed in aluminum pads to avoid
performance slow-downs caused by the redistribution layer.
The wafer-level-processed stacked package comprises four
512-Mbit dual-date-rate (DDR2) DRAM chips for 2 Gbits of
high-density memory. The DRAMs are stacked and interconnected
with TSVs to form a 4-Gbyte dual in-line memory
module (DIMM).
In contrast to wire-bonding techniques, this proprietary technology
forms laser-cut, micron-sized holes vertically through
the silicon and connects the memory circuits directly with copper
filling. A proprietary wafer-thinning technique helps eliminate
warped die in the low-profile package.
Meanwhile, WSP has advanced even further with Tezzaron's
FaStack wafer-stacking technology. It allows for the stacking of
sensor, signal-conditioning, memory, and processor chips on a
thin 3D package (Fig. 1).
Even printed-circuit-board (PCB) technology has gone 3D.
Panasonic Electric Works' microscopic integrated processing
technology (MIPTEC) makes it possible to form 3D PCBs on
an injection-molded substrate using fine-pitch laser patterning.
Panasonic claims MIPTEC enables the development of any
number of devices that require flexibility, miniaturization, and
optical, electrical, and thermal properties.
A common challenge to all 3D packaging is creating the right
interconnect technology. Ziptronix's high-yield direct-bondinterconnect
(DBI) technology can be implemented in a die-towafer
or a wafer-to-wafer format. It supports an interconnect
pitch of less than 10 µm with typical interconnect widths of 2
µm and alignment accuracy of 1 µm.
Sematech, a chip-making consortium, believes the interconnect
challenge is crucial. It has opened up membership in its 3D
interconnect program to suppliers, chip makers, assembly and
packaging companies, and other participants. Launched in
2005, the program has been drafted for the International Technology
Roadmap for Semiconductors (ITRS). TSVs represent
one of the program's focus areas.
Continued on page 2.