Installation considerations: After selecting an ESD suppressor whose suppression and electrical characteristics (leakage current, capacitance) are a good match for the circuit parameters, another choice remains: Where on the board should the suppressor be in-stalled to optimize the ESD protection for the circuit? "Optimized" ESD protection means that the protected chip sees as little of the ESD transient as possible.
High-speed signals and transients (like ESD) bring another parasitic characteristic into play—inductance. Of specific interest is the parasitic inductance of the board traces that are used as interconnects between the connector, the chip, and any support components. Similar to the capacitance effects, the inductance presented by board traces won't affect low-frequency signals. At high speeds, however, the inductance will present an impedance component that can affect signal integrity. Recall the formula for inductive reactance: XL = ?L. This can also be written as: XL = 2pfL.
A small amount of trace inductance can translate into a substantial amount of impedance when a high-frequency signal like ESD is run through it. Designers can take advantage of this by putting as much distance as possible between the ESD suppressor and the protected chip. Refer to Figure 3, where the following inductance values are represented:
- L1—between the connector and the ESD suppressor
- L2—between the ESD suppressor and the I/O pin of the chip
- L3—between the I/O line and the ESD suppressor (stub trace)
In essence, the inductance attributable to L2 will dissipate the energy of the ESD pulse that remains after the clamping action of the ESD suppressor. Attenuation of the ESD pulse's voltage and current take place as the energy is stored and dissipated in the electromagnetic field around the board trace. Note that there's an inverse relationship between the length of board trace and ESD pulse energy that finally arrives at the chip's I/O pin. As the length of the trace increases, the strength of the ESD pulse (seen at the chip) decreases. The decreased ESD pulse translates into reduced stress on the chip.
The plots in Figure 4 show the voltage-versus-time values measured at two locations on a test board. They help us to understand the effects of where the ESD suppression device is placed. In this example, the suppressor was installed at the connector, the entry point for ESD transients.
The blue waveform shows the voltage measured on the I/O line, at the location of the ESD suppressor. The suppressor has responded to the 1000-V transmission-line pulser's pulse with a measured peak voltage of approximately 350 V and a "clamping," or holding, voltage of about 75 V.
Compare this to the green waveform, which shows the ESD pulse that actually gets to the IC. In this case, a 3-in. long trace (L2) connected the ESD suppressor site and the input pad for the IC. Note that the measured peak voltage has been reduced to 60 V and the "clamping" voltage is about 25 V.
What does this mean? For the circuit designer, this provides a tactic for minimizing the amount of ESD experienced on the I/O inputs of the ICs and ASICs. Increasing the amount of trace length between the ESD suppressor and the chip can dramatically reduce how much stress the IC experiences. Referring to Figure 3, this means that making the trace longer will increase the L2 value.
Plainly speaking, the ESD suppressor should be located directly behind the connector. It should be the first board-level component that the ESD transient encounters. Then, to the extent that it's practical, any chip to be protected should be located as far away as possible. As demonstrated in Figure 4, this tactic will drastically reduce the stress that the integrated circuitry experiences. The following list is arranged to show the relative preference of ESD suppressor installation locations. The optimal location is listed first, and the least preferred site is listed last:
- Inside connectors that are the gateway in the system shielding (chassis)
- At the point where circuit-board traces interact with the pins of the connector
- On the circuit board immediately behind the connector
- On robust, unprotected lines that may efficiently couple to I/O lines
- Before a series resistive element on a data line
- Before a fan-out point on a data line
- Near the IC and/or ASIC
Another placement concern is the distance from the board trace to the ESD suppressor (L3 in Figure 3). The goal is to minimize this distance. The inductance associated with the trace, and any parasitic package inductance, will insert impedance in the protection circuit.
In essence, the ESD suppressor be-comes more "isolated" from the signal line that it's protecting as its distance from the line increases. Remember that the chip will experience the ESD voltage across the suppressor plus the voltage across the trace impedance. The ideal solder-pad placement would be right on top of the data line. If this isn't possible, then this distance should be minimized.
Finally, the chassis (frame) ground should be the ESD reference, not the signal (digital) ground (Fig. 3, again). The objective is to transfer the ESD out of the signal environment. By referencing the ESD TVS protection device to chassis ground, unintentional noise effects, like ground bounce, can be avoided. The goal is to keep the signal (data) environment as clean as possible.