Additionally, these methods can be applied in either 2D or 3D model
development. The 2D applications yield inductance, capacitance, and possibly
resistance per-unit-length data for a 2D cross-section of the conductor
structure. The characteristic impedance can be calculated from the L and
C data representing a typical cross-section.
A boundary-element-based program in 2D, for example, makes discrete elements of the surface (boundary) of the conductor. It calculates the charge distribution, assuming a known potential on each conductor, and that only surface currents exist. The total charge can then be calculated for each conductor, and the capacitance inferred from its definition as a ratio of the charge to potential difference. The inductance is usually calculated from the inverse of the C matrix, assuming unity dielectric.
This approach implies no currents internal to the conductors, and hence,
no internal inductance (which is usually small for nonmagnetic conductors
at frequencies typical of digital applications). Finite-element applications
for 2D make discrete elements of the total cross-section. They can determine
more information on current distribution over the lead cross section,
and therefore, the internal inductance and resistance as a function of
frequency. Note that the 2D applications assume a predefined current return
path built into the inductance data.
The finite-element method may also be applied to 3D problems by using
discrete volume elements. The PEEC approach, which uses discrete current
filaments or paths, is also popular for 3D applications. These methods
can supply information on the current distribution on planes and, thus,
a full 3D picture of the inductance of all paths. The 3D tools allow the
definition of current sources and sinks on the planes, giving the effects
of these conditions on the operating characteristics of the package.
A more exhaustive analysis is performed by full-wave tools, which model
how electromagnetic fields are propagated through the package structure.
Because full-wave tools essentially solve a discrete form of Maxwell's
equations; they are very thorough, but run relatively slowly. Even as
computing power grows in the future, full-wave tools will continue to
run slowly because the packages they model will become increasingly complex.
At the same time, because they are so exhaustive in their analysis, full-wave
tools provide high precision in the verification of other tools.
Package Data
Chip designers must define certain basic information about the expected
package electrical characteristics by supplying the knowledge they have
about signal behavior, whether it's based on device simulation or previous
designs. This information generally falls into two areas: power requirements
and signaling specifications.
Power requirements include worst-case peak current levels, when all
I/Os switch simultaneously, and rise times for core and output buffers.
In addition, the chip designer needs to specify a noise budget showing
how much noise is permissible in the PWR and GND at the chip. While zero
noise is desirable, it is also unachievable, making the budget is an essential
part of the package design.
These requirements allow the calculation of LEFF, which in
advanced designs today, may be on the order of a few picohenries. LEFF,
in turn, allows the package designer to determine how many PWR and GND
paths are necessary, or whether PWR and GND planes are needed at all.
Important signaling specifications include how many single-ended and
differential signals are required, and where they are located. High-speed
signals may also require a GND plane to be specified for impedance control.
In addition, the designer should specify how much isolation is required
between inputs and outputs, defining how much crosstalk can be fed back
to the inputs from the outputs. This crosstalk budget may be expressed
as a percentage of the signal or in dB. Based on these specifications,
the package designer can determine how much shielding to introduce through
GND planes, and whether or not to isolate signals by relocating outputs.
Evaluating Vendor Support
Designers undertake complex digital or mixed-signal designs should be
sure that the package vendors with whom they deal have access to a set
of well-established, sophisticated tools that model the electrical, mechanical,
and thermal characteristics of packages. Eventually, all of these models
may operate together in a single integrated tool, but today the complexities
of modeling make it very difficult to calculate electrical, mechanical,
and thermal factors at the same time with the desired accuracy.
The electrical tools should include all pertinent paths in the model
description. They also should take inputs directly from chip-design software
and output them in a usable manner to simulation software such as Spice.
At the minimum, the tools must be able to calculate RLC factors, with
attenuation, timing, and scattering parameters at high frequencies as
high priorities. Access to full-wave tools is also a desirable capability
in the package vendor's tool chest.
Industry Vendors
Other factors can indicate how seriously the vendor views the electrical
issues of packaging. Vendor participation in standards organizations such
as JEDEC helps provide a common ground for package characterization throughout
the industry. Vendors can also take part in industry efforts to improve
package modeling tools. For instance, the Semiconductor Research Corp.,
Research Triangle Park, N.C. with funding and guidance from industry vendors,
contributes to university research in package measurement and modeling.
As a result, many of the best modeling tools come from research done in
universities, notably the University of Arizona at Tucson.
Vendors must also dedicate resources to the extensive measurement and
analysis required for model verification. Much of this verification is
inferential, because the critical factors often cannot be measured directly.
Texas Instruments, for instance, devotes an entire lab to this type of
measurement to close the loop on the parametric information used in package
models.
Ensuring Design Performance
Eventually, electrical modeling tools will be combined with layout tools
to optimize the operation of the chip within its package automatically.
However, until then, and even afterward to some extent, chip designers
must be aware that the package is an electrical environment, and that
their products can function more efficiently if they are designed with
environmental factors taken into account. Package modeling software, combined
with a good understanding of signal characteristics within the package,
can help ensure that good designs perform as they should.
Additionally, these methods can be applied in either 2D or 3D model
development. The 2D applications yield inductance, capacitance, and possibly
resistance per-unit-length data for a 2D cross-section of the conductor
structure. The characteristic impedance can be calculated from the L and
C data representing a typical cross-section.
A boundary-element-based program in 2D, for example, makes discrete elements of the surface (boundary) of the conductor. It calculates the charge distribution, assuming a known potential on each conductor, and that only surface currents exist. The total charge can then be calculated for each conductor, and the capacitance inferred from its definition as a ratio of the charge to potential difference. The inductance is usually calculated from the inverse of the C matrix, assuming unity dielectric.
This approach implies no currents internal to the conductors, and hence,
no internal inductance (which is usually small for nonmagnetic conductors
at frequencies typical of digital applications). Finite-element applications
for 2D make discrete elements of the total cross-section. They can determine
more information on current distribution over the lead cross section,
and therefore, the internal inductance and resistance as a function of
frequency. Note that the 2D applications assume a predefined current return
path built into the inductance data.
The finite-element method may also be applied to 3D problems by using
discrete volume elements. The PEEC approach, which uses discrete current
filaments or paths, is also popular for 3D applications. These methods
can supply information on the current distribution on planes and, thus,
a full 3D picture of the inductance of all paths. The 3D tools allow the
definition of current sources and sinks on the planes, giving the effects
of these conditions on the operating characteristics of the package.
A more exhaustive analysis is performed by full-wave tools, which model
how electromagnetic fields are propagated through the package structure.
Because full-wave tools essentially solve a discrete form of Maxwell's
equations; they are very thorough, but run relatively slowly. Even as
computing power grows in the future, full-wave tools will continue to
run slowly because the packages they model will become increasingly complex.
At the same time, because they are so exhaustive in their analysis, full-wave
tools provide high precision in the verification of other tools.
Package Data
Chip designers must define certain basic information about the expected
package electrical characteristics by supplying the knowledge they have
about signal behavior, whether it's based on device simulation or previous
designs. This information generally falls into two areas: power requirements
and signaling specifications.
Power requirements include worst-case peak current levels, when all
I/Os switch simultaneously, and rise times for core and output buffers.
In addition, the chip designer needs to specify a noise budget showing
how much noise is permissible in the PWR and GND at the chip. While zero
noise is desirable, it is also unachievable, making the budget is an essential
part of the package design.
These requirements allow the calculation of LEFF, which in
advanced designs today, may be on the order of a few picohenries. LEFF,
in turn, allows the package designer to determine how many PWR and GND
paths are necessary, or whether PWR and GND planes are needed at all.
Important signaling specifications include how many single-ended and
differential signals are required, and where they are located. High-speed
signals may also require a GND plane to be specified for impedance control.
In addition, the designer should specify how much isolation is required
between inputs and outputs, defining how much crosstalk can be fed back
to the inputs from the outputs. This crosstalk budget may be expressed
as a percentage of the signal or in dB. Based on these specifications,
the package designer can determine how much shielding to introduce through
GND planes, and whether or not to isolate signals by relocating outputs.
Evaluating Vendor Support
Designers undertake complex digital or mixed-signal designs should be
sure that the package vendors with whom they deal have access to a set
of well-established, sophisticated tools that model the electrical, mechanical,
and thermal characteristics of packages. Eventually, all of these models
may operate together in a single integrated tool, but today the complexities
of modeling make it very difficult to calculate electrical, mechanical,
and thermal factors at the same time with the desired accuracy.
The electrical tools should include all pertinent paths in the model
description. They also should take inputs directly from chip-design software
and output them in a usable manner to simulation software such as Spice.
At the minimum, the tools must be able to calculate RLC factors, with
attenuation, timing, and scattering parameters at high frequencies as
high priorities. Access to full-wave tools is also a desirable capability
in the package vendor's tool chest.
Industry Vendors
Other factors can indicate how seriously the vendor views the electrical
issues of packaging. Vendor participation in standards organizations such
as JEDEC helps provide a common ground for package characterization throughout
the industry. Vendors can also take part in industry efforts to improve
package modeling tools. For instance, the Semiconductor Research Corp.,
Research Triangle Park, N.C. with funding and guidance from industry vendors,
contributes to university research in package measurement and modeling.
As a result, many of the best modeling tools come from research done in
universities, notably the University of Arizona at Tucson.
Vendors must also dedicate resources to the extensive measurement and
analysis required for model verification. Much of this verification is
inferential, because the critical factors often cannot be measured directly.
Texas Instruments, for instance, devotes an entire lab to this type of
measurement to close the loop on the parametric information used in package
models.
Ensuring Design Performance
Eventually, electrical modeling tools will be combined with layout tools
to optimize the operation of the chip within its package automatically.
However, until then, and even afterward to some extent, chip designers
must be aware that the package is an electrical environment, and that
their products can function more efficiently if they are designed with
environmental factors taken into account. Package modeling software, combined
with a good understanding of signal characteristics within the package,
can help ensure that good designs perform as they should.